+2020-06-22 Alex Coplan <alex.coplan@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SHA2): Normalize.
+ (AARCH64_FEATURE_AES): Likewise.
+ (AARCH64_FEATURE_V8_4): Likewise.
+ (AARCH64_FEATURE_SM4): Likewise.
+ (AARCH64_FEATURE_SHA3): Likewise.
+ (AARCH64_FEATURE_V8): Likewise.
+ (AARCH64_FEATURE_V8_2): Likewise.
+ (AARCH64_FEATURE_V8_3): Likewise.
+ (AARCH64_FEATURE_FP): Likewise.
+ (AARCH64_FEATURE_SIMD): Likewise.
+ (AARCH64_FEATURE_CRC): Likewise.
+ (AARCH64_FEATURE_LSE): Likewise.
+ (AARCH64_FEATURE_PAN): Likewise.
+ (AARCH64_FEATURE_LOR): Likewise.
+ (AARCH64_FEATURE_RDMA): Likewise.
+ (AARCH64_FEATURE_V8_1): Likewise.
+ (AARCH64_FEATURE_F16): Likewise.
+ (AARCH64_FEATURE_RAS): Likewise.
+ (AARCH64_FEATURE_PROFILE): Likewise.
+ (AARCH64_FEATURE_SVE): Likewise.
+ (AARCH64_FEATURE_RCPC): Likewise.
+ (AARCH64_FEATURE_COMPNUM): Likewise.
+ (AARCH64_FEATURE_DOTPROD): Likewise.
+ (AARCH64_FEATURE_F16_FML): Likewise.
+ (AARCH64_FEATURE_V8_5): Likewise.
+ (AARCH64_FEATURE_V8_6): Likewise.
+ (AARCH64_FEATURE_BFLOAT16): Likewise.
+ (AARCH64_FEATURE_FLAGMANIP): Likewise.
+ (AARCH64_FEATURE_FRINTTS): Likewise.
+ (AARCH64_FEATURE_SB): Likewise.
+ (AARCH64_FEATURE_PREDRES): Likewise.
+ (AARCH64_FEATURE_CVADP): Likewise.
+ (AARCH64_FEATURE_RNG): Likewise.
+ (AARCH64_FEATURE_BTI): Likewise.
+ (AARCH64_FEATURE_SCXTNUM): Likewise.
+ (AARCH64_FEATURE_ID_PFR2): Likewise.
+ (AARCH64_FEATURE_SSBS): Likewise.
+ (AARCH64_FEATURE_MEMTAG): Likewise.
+ (AARCH64_FEATURE_TME): Likewise.
+ (AARCH64_FEATURE_I8MM): Likewise.
+ (AARCH64_FEATURE_F32MM): Likewise.
+ (AARCH64_FEATURE_F64MM): Likewise.
+ (AARCH64_FEATURE_SVE2): Likewise.
+ (AARCH64_FEATURE_SVE2_AES): Likewise.
+ (AARCH64_FEATURE_SVE2_BITPERM): Likewise.
+ (AARCH64_FEATURE_SVE2_SM4): Likewise.
+ (AARCH64_FEATURE_SVE2_SHA3): Likewise.
+
+2020-06-22 Saagar Jha <saagar@saagarjha.com>
+
+ * mach-o/loader.h: Add declarations of two new Mach-O load
+ commands.
+
+2020-06-22 Nelson Chu <nelson.chu@sifive.com>
+
+ * opcode/riscv.h (riscv_get_priv_spec_class): Move the function
+ forward declarations to bfd/elfxx-riscv.h.
+ (riscv_get_priv_spec_name): Likewise.
+
+2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
+
+ * elf/xtensa.h (xtensa_abi_choice): New declaration.
+
+2020-06-12 Roland McGrath <mcgrathr@google.com>
+
+ * bfdlink.h (struct bfd_link_info): New field start_stop_visibility.
+
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * opcode/riscv-opc.h: Update the defined versions of CSR from
+ PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the
+ MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
+ * opcode/riscv.h (enum riscv_priv_spec_class): Remove
+ PRIV_SPEC_CLASS_1P9.
+
+2020-06-11 Alex Coplan <alex.coplan@arm.com>
+
+ * opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
+ describing system registers.
+
+2020-06-11 Alan Modra <amodra@gmail.com>
+
+ * elf/mips.h (Elf32_RegInfo): Use fixed width integer types.
+ (Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise.
+
+2020-06-06 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc64.h (elf_ppc64_reloc_type): Rename
+ R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
+ R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
+ R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
+ R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
+
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * opcode/cgen.h: Get an `endian' argument in both
+ cgen_get_insn_value and cgen_put_insn_value.
+
+2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
+
+ * opcode/cgen.h (enum cgen_cpu_open_arg): New value
+ CGEN_CPU_OPEN_INSN_ENDIAN.
+
+2020-06-03 Nelson Chu <nelson.chu@sifive.com>
+
+ * opcode/riscv.h: Remove #include "bfd.h". And change the return
+ types of riscv_get_isa_spec_class and riscv_get_priv_spec_class
+ from bfd_boolean to int.
+
2020-05-28 Alan Modra <amodra@gmail.com>
PR 26044
projects / deliverable / binutils-gdb.git / blobdiff