gold, ld: Implement -z start-stop-visibility=... option.
[deliverable/binutils-gdb.git] / include / ChangeLog
index 5c0a82b5f8e851f68c20ceccd31dced46d5012b0..f30e5e2a24a0c17192c33aacae26dc3d5bb89acc 100644 (file)
@@ -1,3 +1,43 @@
+2020-06-12  Roland McGrath  <mcgrathr@google.com>
+
+       * bfdlink.h (struct bfd_link_info): New field start_stop_visibility.
+
+2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
+
+       * opcode/riscv-opc.h: Update the defined versions of CSR from
+       PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1.  Also, drop the
+       MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
+       * opcode/riscv.h (enum riscv_priv_spec_class): Remove
+       PRIV_SPEC_CLASS_1P9.
+
+2020-06-11  Alex Coplan  <alex.coplan@arm.com>
+
+       * opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
+       describing system registers.
+
+2020-06-11  Alan Modra  <amodra@gmail.com>
+
+       * elf/mips.h (Elf32_RegInfo): Use fixed width integer types.
+       (Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise.
+
+2020-06-06  Alan Modra  <amodra@gmail.com>
+
+       * elf/ppc64.h (elf_ppc64_reloc_type): Rename
+       R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
+       R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
+       R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
+       R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
+
+2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * opcode/cgen.h: Get an `endian' argument in both
+       cgen_get_insn_value and cgen_put_insn_value.
+
+2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
+
+       * opcode/cgen.h (enum cgen_cpu_open_arg): New value
+       CGEN_CPU_OPEN_INSN_ENDIAN.
+
 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 
        * opcode/riscv.h: Remove #include "bfd.h".  And change the return
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