MIPS16: Handle non-extensible instructions correctly

[deliverable/binutils-gdb.git] / include / ChangeLog

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+2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (INSN2_SHORT_ONLY): New macro.
+
+2016-12-21  Alan Modra  <amodra@gmail.com>
+
+       * coff/pe.h: Fix comment chars with high bit set.
+       * opcode/xgate.h: Likewise.
+
+2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (mips_opcode_32bit_p): New inline function.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
+       (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
+       (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
+       (EF_RISCV_FLOAT_ABI_QUAD): Define.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+           Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+       * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
+
+2016-12-16  fincs  <fincs.alt1@gmail.com>
+
+       * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
+       typedef as `elf_internal_abiflags_v0'.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+       * opcode/aarch64.h (aarch64_operand_class): Remove
+       AARCH64_OPND_CLASS_CP_REG.
+       (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
+       AARCH64_OPND_Cm to AARCH64_OPND_CRm.
+       (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
+
+2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h: Remove references to `>' operand code.
+
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
+
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (ASE_DSPR3): Add a comment.
+
 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
        * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.