i.MXC family: Adding timer support

[deliverable/linux.git] / include / asm-arm / arch-mxc / mxc.h

diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a5e6340d8139a3f2e29b74a229ce7..1df4e2f249204ded68246fe84dee74db8de9fc72 100644 (file)
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
 /*
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
  */
 
 #ifndef __ASM_ARCH_MXC_H__
@@ -20,97 +29,6 @@
 # define cpu_is_mx31() (0)
 #endif
 
-/*
- *****************************************
- * GPT  Register definitions             *
- *****************************************
- */
-#define MXC_GPT_GPTCR          IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
-#define MXC_GPT_GPTPR          IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
-#define MXC_GPT_GPTSR          IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
-#define MXC_GPT_GPTIR          IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
-#define MXC_GPT_GPTOCR1                IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
-#define MXC_GPT_GPTOCR2                IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
-#define MXC_GPT_GPTOCR3                IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
-#define MXC_GPT_GPTICR1                IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
-#define MXC_GPT_GPTICR2                IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
-#define MXC_GPT_GPTCNT         IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-
-/* GPT Control register bit definitions */
-#define GPTCR_FO3                      (1 << 31)
-#define GPTCR_FO2                      (1 << 30)
-#define GPTCR_FO1                      (1 << 29)
-
-#define GPTCR_OM3_SHIFT                        26
-#define GPTCR_OM3_MASK                 (7 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_DISCONNECTED         (0 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_TOGGLE               (1 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_CLEAR                        (2 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_SET                  (3 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_GENERATE_LOW         (7 << GPTCR_OM3_SHIFT)
-
-#define GPTCR_OM2_SHIFT                        23
-#define GPTCR_OM2_MASK                 (7 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_DISCONNECTED         (0 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_TOGGLE               (1 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_CLEAR                        (2 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_SET                  (3 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_GENERATE_LOW         (7 << GPTCR_OM2_SHIFT)
-
-#define GPTCR_OM1_SHIFT                        20
-#define GPTCR_OM1_MASK                 (7 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_DISCONNECTED         (0 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_TOGGLE               (1 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_CLEAR                        (2 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_SET                  (3 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_GENERATE_LOW         (7 << GPTCR_OM1_SHIFT)
-
-#define GPTCR_IM2_SHIFT                        18
-#define GPTCR_IM2_MASK                 (3 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_DISABLE      (0 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_RISING       (1 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_FALLING      (2 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_BOTH         (3 << GPTCR_IM2_SHIFT)
-
-#define GPTCR_IM1_SHIFT                        16
-#define GPTCR_IM1_MASK                 (3 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_DISABLE      (0 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_RISING       (1 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_FALLING      (2 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_BOTH         (3 << GPTCR_IM1_SHIFT)
-
-#define GPTCR_SWR                      (1 << 15)
-#define GPTCR_FRR                      (1 << 9)
-
-#define GPTCR_CLKSRC_SHIFT             6
-#define GPTCR_CLKSRC_MASK              (7 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_NOCLOCK           (0 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_HIGHFREQ          (2 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLKIN             (3 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLK32K            (7 << GPTCR_CLKSRC_SHIFT)
-
-#define GPTCR_STOPEN                   (1 << 5)
-#define GPTCR_DOZEN                    (1 << 4)
-#define GPTCR_WAITEN                   (1 << 3)
-#define GPTCR_DBGEN                    (1 << 2)
-
-#define GPTCR_ENMOD                    (1 << 1)
-#define GPTCR_ENABLE                   (1 << 0)
-
-#define GPTSR_OF1                      (1 << 0)
-#define GPTSR_OF2                      (1 << 1)
-#define GPTSR_OF3                      (1 << 2)
-#define GPTSR_IF1                      (1 << 3)
-#define GPTSR_IF2                      (1 << 4)
-#define GPTSR_ROV                      (1 << 5)
-
-#define GPTIR_OF1IE                    GPTSR_OF1
-#define GPTIR_OF2IE                    GPTSR_OF2
-#define GPTIR_OF3IE                    GPTSR_OF3
-#define GPTIR_IF1IE                    GPTSR_IF1
-#define GPTIR_IF2IE                    GPTSR_IF2
-#define GPTIR_ROVIE                    GPTSR_ROV
-
 /*
  *****************************************
  * AVIC Registers                        *