x86: change x86 to use generic find_next_bit

[deliverable/linux.git] / include / asm-x86 / bitops.h

diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
index c6dd7e259b469b2f41579dbe18859e359e869c64..31e408de90c677735b95c016a45e388c5df02073 100644 (file)
--- a/include/asm-x86/bitops.h
+++ b/include/asm-x86/bitops.h
@@ -23,10 +23,13 @@
 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
 /* Technically wrong, but this avoids compilation errors on some gcc
    versions. */
-#define ADDR "=m" (*(volatile long *) addr)
+#define ADDR "=m" (*(volatile long *)addr)
+#define BIT_ADDR "=m" (((volatile int *)addr)[nr >> 5])
 #else
 #define ADDR "+m" (*(volatile long *) addr)
+#define BIT_ADDR "+m" (((volatile int *)addr)[nr >> 5])
 #endif
+#define BASE_ADDR "m" (*(volatile int *)addr)
 
 /**
  * set_bit - Atomically set a bit in memory
@@ -43,11 +46,9 @@
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
-static inline void set_bit(int nr, volatile unsigned long *addr)
+static inline void set_bit(int nr, volatile void *addr)
 {
-       asm volatile(LOCK_PREFIX "bts %1,%0"
-                    : ADDR
-                    : "Ir" (nr) : "memory");
+       asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory");
 }
 
 /**
@@ -59,7 +60,7 @@ static inline void set_bit(int nr, volatile unsigned long *addr)
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
-static inline void __set_bit(int nr, volatile unsigned long *addr)
+static inline void __set_bit(int nr, volatile void *addr)
 {
        asm volatile("bts %1,%0"
                     : ADDR
@@ -77,11 +78,9 @@ static inline void __set_bit(int nr, volatile unsigned long *addr)
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
-static inline void clear_bit(int nr, volatile unsigned long *addr)
+static inline void clear_bit(int nr, volatile void *addr)
 {
-       asm volatile(LOCK_PREFIX "btr %1,%0"
-                    : ADDR
-                    : "Ir" (nr));
+       asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
 }
 
 /*
@@ -92,15 +91,15 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
  * clear_bit() is atomic and implies release semantics before the memory
  * operation. It can be used for an unlock.
  */
-static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
+static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
 {
        barrier();
        clear_bit(nr, addr);
 }
 
-static inline void __clear_bit(int nr, volatile unsigned long *addr)
+static inline void __clear_bit(int nr, volatile void *addr)
 {
-       asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
+       asm volatile("btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
 }
 
 /*
@@ -115,7 +114,7 @@ static inline void __clear_bit(int nr, volatile unsigned long *addr)
  * No memory barrier is required here, because x86 cannot reorder stores past
  * older loads. Same principle as spin_unlock.
  */
-static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
+static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
 {
        barrier();
        __clear_bit(nr, addr);
@@ -133,9 +132,9 @@ static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
-static inline void __change_bit(int nr, volatile unsigned long *addr)
+static inline void __change_bit(int nr, volatile void *addr)
 {
-       asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
+       asm volatile("btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
 }
 
 /**
@@ -147,10 +146,9 @@ static inline void __change_bit(int nr, volatile unsigned long *addr)
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
-static inline void change_bit(int nr, volatile unsigned long *addr)
+static inline void change_bit(int nr, volatile void *addr)
 {
-       asm volatile(LOCK_PREFIX "btc %1,%0"
-                    : ADDR : "Ir" (nr));
+       asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
 }
 
 /**
@@ -161,14 +159,12 @@ static inline void change_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int test_and_set_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
        asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
-                    "sbb %0,%0"
-                    : "=r" (oldbit), ADDR
-                    : "Ir" (nr) : "memory");
+                    "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 
        return oldbit;
 }
@@ -180,7 +176,7 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
  *
  * This is the same as test_and_set_bit on x86.
  */
-static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
+static inline int test_and_set_bit_lock(int nr, volatile void *addr)
 {
        return test_and_set_bit(nr, addr);
 }
@@ -194,14 +190,13 @@ static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
-static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
-       asm("bts %2,%1\n\t"
-           "sbb %0,%0"
-           : "=r" (oldbit), ADDR
-           : "Ir" (nr));
+       asm volatile("bts %2,%3\n\t"
+                    "sbb %0,%0"
+                    : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
        return oldbit;
 }
 
@@ -213,14 +208,13 @@ static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int test_and_clear_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
        asm volatile(LOCK_PREFIX "btr %2,%1\n\t"
                     "sbb %0,%0"
-                    : "=r" (oldbit), ADDR
-                    : "Ir" (nr) : "memory");
+                    : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 
        return oldbit;
 }
@@ -234,26 +228,24 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
-static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
-       asm volatile("btr %2,%1\n\t"
+       asm volatile("btr %2,%3\n\t"
                     "sbb %0,%0"
-                    : "=r" (oldbit), ADDR
-                    : "Ir" (nr));
+                    : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
        return oldbit;
 }
 
 /* WARNING: non atomic and it can be reordered! */
-static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_change_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
-       asm volatile("btc %2,%1\n\t"
+       asm volatile("btc %2,%3\n\t"
                     "sbb %0,%0"
-                    : "=r" (oldbit), ADDR
-                    : "Ir" (nr) : "memory");
+                    : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
 
        return oldbit;
 }
@@ -266,31 +258,32 @@ static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+static inline int test_and_change_bit(int nr, volatile void *addr)
 {
        int oldbit;
 
        asm volatile(LOCK_PREFIX "btc %2,%1\n\t"
                     "sbb %0,%0"
-                    : "=r" (oldbit), ADDR
-                    : "Ir" (nr) : "memory");
+                    : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 
        return oldbit;
 }
 
-static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
+static inline int constant_test_bit(int nr, const volatile void *addr)
 {
-       return ((1UL << (nr % BITS_PER_LONG)) & (addr[nr / BITS_PER_LONG])) != 0;
+       return ((1UL << (nr % BITS_PER_LONG)) &
+               (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
 }
 
-static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
+static inline int variable_test_bit(int nr, volatile const void *addr)
 {
        int oldbit;
 
-       asm volatile("bt %2,%1\n\t"
+       asm volatile("bt %2,%3\n\t"
                     "sbb %0,%0"
                     : "=r" (oldbit)
-                    : "m" (*addr), "Ir" (nr));
+                    : "m" (((volatile const int *)addr)[nr >> 5]),
+                      "Ir" (nr), BASE_ADDR);
 
        return oldbit;
 }
@@ -309,8 +302,16 @@ static int test_bit(int nr, const volatile unsigned long *addr);
         constant_test_bit((nr),(addr)) :       \
         variable_test_bit((nr),(addr)))
 
+#undef BASE_ADDR
+#undef BIT_ADDR
 #undef ADDR
 
+unsigned long find_next_bit(const unsigned long *addr,
+               unsigned long size, unsigned long offset);
+unsigned long find_next_zero_bit(const unsigned long *addr,
+               unsigned long size, unsigned long offset);
+
+
 #ifdef CONFIG_X86_32
 # include "bitops_32.h"
 #else