/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
- Copyright (C) 1991-2013 Free Software Foundation, Inc.
+ Copyright (C) 1991-2019 Free Software Foundation, Inc.
This file is part of the GNU C Library.
#define __AND_CLOBBER_CC , "cc"
#endif /* __GNUC__ < 2 */
+#if defined (__aarch64__)
+
+#if W_TYPE_SIZE == 32
+#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
+#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif /* W_TYPE_SIZE == 32 */
+
+#if W_TYPE_SIZE == 64
+#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clzll (X))
+#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctzll (X))
+#define COUNT_LEADING_ZEROS_0 64
+#endif /* W_TYPE_SIZE == 64 */
+
+#endif /* __aarch64__ */
+
#if defined (__alpha) && W_TYPE_SIZE == 64
+/* There is a bug in g++ before version 5 that
+ errors on __builtin_alpha_umulh. */
+#if !defined(__cplusplus) || __GNUC__ >= 5
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(pl) = __m0 * __m1; \
} while (0)
#define UMUL_TIME 46
+#endif /* !c++ */
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UDItype __r; \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \
- "rIJ" ((USItype) (bh)), \
+ "rICal" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
- "rIJ" ((USItype) (bl)))
+ "rICal" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \
- "rIJ" ((USItype) (bh)), \
+ "rICal" ((USItype) (bh)), \
"r" ((USItype) (al)), \
- "rIJ" ((USItype) (bl)))
+ "rICal" ((USItype) (bl)))
#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
#ifdef __ARC_NORM__
} \
while (0)
#define COUNT_LEADING_ZEROS_0 32
-#endif
-#endif
+#endif /* __ARC_NORM__ */
+#endif /* __arc__ */
#if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
&& W_TYPE_SIZE == 32
#define UDIV_TIME 40
#endif /* 80x86 */
-#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
+#if defined (__x86_64__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
: "=r" ((UDItype) (sh)), \
#define UMUL_TIME 10
#define UDIV_TIME 100
-#if (__mips == 32 || __mips == 64) && ! __mips16
+#if (__mips == 32 || __mips == 64) && ! defined (__mips16)
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
#define COUNT_LEADING_ZEROS_0 32
#endif
#endif /* __mips__ */
-#if defined (__ns32000__) && W_TYPE_SIZE == 32
-#define umul_ppmm(w1, w0, u, v) \
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __asm__ ("meid %2,%0" \
- : "=g" (__xx.__ll) \
- : "%0" ((USItype) (u)), \
- "g" ((USItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
-#define __umulsidi3(u, v) \
- ({UDItype __w; \
- __asm__ ("meid %2,%0" \
- : "=g" (__w) \
- : "%0" ((USItype) (u)), \
- "g" ((USItype) (v))); \
- __w; })
-#define udiv_qrnnd(q, r, n1, n0, d) \
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
- __asm__ ("deid %2,%0" \
- : "=g" (__xx.__ll) \
- : "0" (__xx.__ll), \
- "g" ((USItype) (d))); \
- (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
-#define count_trailing_zeros(count,x) \
- do { \
- __asm__ ("ffsd %2,%0" \
- : "=r" ((USItype) (count)) \
- : "0" ((USItype) 0), \
- "r" ((USItype) (x))); \
- } while (0)
-#endif /* __ns32000__ */
-
/* FIXME: We should test _IBMR2 here when we add assembly support for the
system vendor compilers.
FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
} while (0)
#endif
-#if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
+#if defined(__riscv)
+#ifdef __riscv_mul
+#define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v))
+#define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b))
+#else
+#if __riscv_xlen == 32
+ #define MULUW3 "call __mulsi3"
+#elif __riscv_xlen == 64
+ #define MULUW3 "call __muldi3"
+#else
+#error unsupport xlen
+#endif /* __riscv_xlen */
+/* We rely on the fact that MULUW3 doesn't clobber the t-registers.
+ It can get better register allocation result. */
+#define __muluw3(a, b) \
+ ({ \
+ register UWtype __op0 asm ("a0") = a; \
+ register UWtype __op1 asm ("a1") = b; \
+ asm volatile (MULUW3 \
+ : "+r" (__op0), "+r" (__op1) \
+ : \
+ : "ra", "a2", "a3"); \
+ __op0; \
+ })
+#endif /* __riscv_mul */
+#define umul_ppmm(w1, w0, u, v) \
+ do { \
+ UWtype __x0, __x1, __x2, __x3; \
+ UHWtype __ul, __vl, __uh, __vh; \
+ \
+ __ul = __ll_lowpart (u); \
+ __uh = __ll_highpart (u); \
+ __vl = __ll_lowpart (v); \
+ __vh = __ll_highpart (v); \
+ \
+ __x0 = __muluw3 (__ul, __vl); \
+ __x1 = __muluw3 (__ul, __vh); \
+ __x2 = __muluw3 (__uh, __vl); \
+ __x3 = __muluw3 (__uh, __vh); \
+ \
+ __x1 += __ll_highpart (__x0);/* this can't give carry */ \
+ __x1 += __x2; /* but this indeed can */ \
+ if (__x1 < __x2) /* did we get it? */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ \
+ (w1) = __x3 + __ll_highpart (__x1); \
+ (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
+ } while (0)
+#endif /* __riscv */
+
+#if defined(__sh__) && W_TYPE_SIZE == 32
#ifndef __sh1__
#define umul_ppmm(w1, w0, u, v) \
__asm__ ( \
/* This is the same algorithm as __udiv_qrnnd_c. */
#define UDIV_NEEDS_NORMALIZATION 1
+#ifdef __FDPIC__
+/* FDPIC needs a special version of the asm fragment to extract the
+ code address from the function descriptor. __udiv_qrnnd_16 is
+ assumed to be local and not to use the GOT, so loading r12 is
+ not needed. */
+#define udiv_qrnnd(q, r, n1, n0, d) \
+ do { \
+ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
+ __attribute__ ((visibility ("hidden"))); \
+ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
+ __asm__ ( \
+ "mov%M4 %4,r5\n" \
+" swap.w %3,r4\n" \
+" swap.w r5,r6\n" \
+" mov.l @%5,r2\n" \
+" jsr @r2\n" \
+" shll16 r6\n" \
+" swap.w r4,r4\n" \
+" mov.l @%5,r2\n" \
+" jsr @r2\n" \
+" swap.w r1,%0\n" \
+" or r1,%0" \
+ : "=r" (q), "=&z" (r) \
+ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
+ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
+ } while (0)
+#else
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
: "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
: "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
} while (0)
+#endif /* __FDPIC__ */
#define UDIV_TIME 80
#endif /* __sh__ */
-#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
-#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
-#define count_leading_zeros(count, x) \
- do \
- { \
- UDItype x_ = (USItype)(x); \
- SItype c_; \
- \
- __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
- (count) = c_ - 31; \
- } \
- while (0)
-#define COUNT_LEADING_ZEROS_0 32
-#endif
-
#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
&& W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
#define udiv_qrnnd(q, r, nh, nl, d) \
do { \
- USItype __r; \
+ extern UWtype __udiv_w_sdiv (UWtype *, UWtype, UWtype, UWtype); \
+ UWtype __r; \
(q) = __udiv_w_sdiv (&__r, nh, nl, d); \
(r) = __r; \
} while (0)