* cris.h (enum cris_insn_version_usage): Tweak formatting and

[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b8ca48603631879659bd7574d37ed45feefe0a1a..1d790637b06336502365a18ebc2609bd95a783d7 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,59 @@
+2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
+
+       * cris.h (enum cris_insn_version_usage): Tweak formatting and
+       comments.  Remove member cris_ver_sim.  Add members
+       cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
+       cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
+       (struct cris_support_reg, struct cris_cond15): New types.
+       (cris_conds15): Declare.
+       (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
+       (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
+       (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
+       (NOP_Z_BITS): Define in terms of NOP_OPCODE.
+       (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
+       SIZE_FIELD_UNSIGNED.
+
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+       * i386.h (sldx_Suf): Remove.
+       (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
+       (q_FP): Define, implying no REX64.
+       (x_FP, sl_FP): Imply FloatMF.
+       (i386_optab): Split reg and mem forms of moving from segment registers
+       so that the memory forms can ignore the 16-/32-bit operand size
+       distinction. Adjust a few others for Intel mode. Remove *FP uses from
+       all non-floating-point instructions. Unite 32- and 64-bit forms of
+       movsx, movzx, and movd. Adjust floating point operations for the above
+       changes to the *FP macros. Add DefaultSize to floating point control
+       insns operating on larger memory ranges. Remove left over comments
+       hinting at certain insns being Intel-syntax ones where the ones
+       actually meant are already gone.
+
+2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+       * crx.h: Add COPS_REG_INS - Coprocessor Special register
+       instruction type.
+
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+       * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
+       (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
+
+2004-09-11  Theodore A. Roth  <troth@openavr.org>
+
+       * avr.h: Add support for
+       atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
+
+2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
+
+2004-08-24  Dmitry Diky  <diwil@spec.ru>
+
+       * msp430.h (msp430_opc): Add new instructions.
+       (msp430_rcodes): Declare new instructions.
+       (msp430_hcodes): Likewise..
+
 2004-08-13  Nick Clifton  <nickc@redhat.com>
 
        PR/301