+start-sanitize-v850
+Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * v850.h: New file.
+
+end-sanitize-v850
+Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk>
+
+ * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
+ OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+ OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+ OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+ OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+ Defined.
+
+Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
+ a 3 bit space id instead of a 2 bit space id.
+
+start-sanitize-d10v
+Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v.h: Add some additional defines to support the
+ assembler in determining which operations can be done in parallel.
+
+end-sanitize-d10v
+Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (SN): Define.
+ (eepmov.b): Renamed from "eepmov"
+ (nop, bpt, rte, rts, sleep, clrmac): These have no size associated
+ with them.
+
+start-sanitize-d10v
+Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v.h (OPERAND_SHIFT): New operand flag.
+
+Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v.h: Changes for divs, parallel-only instructions, and
+ signed numbers.
+
+Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v.h (pd_reg): Define. Putting the definition here allows
+ the assembler and disassembler to share the same struct.
+
+end-sanitize-d10v
+Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i960.h (i960_opcodes): "halt" takes an argument. From Stephen
+ Williams <steve@icarus.com>.
+
+start-sanitize-d10v
+Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v.h: New file.
+
+end-sanitize-d10v
+Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (band, bclr): Force high bit of immediate nibble to zero.
+
+Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * m68k.h (mcf5200): New macro.
+ Document names of coldfire control registers.
+
+Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (SRC_IN_DST): Define.
+
+ * h8300.h (UNOP3): Mark the register operand in this insn
+ as a source operand, not a destination operand.
+ (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references.
+ (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark
+ register operand with SRC_IN_DST.
+
+Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu>
+
+ * alpha.h: New file.
+
+Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * rs6k.h: Remove obsolete file.
+
+Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
+ fdivp, and fdivrp. Add ffreep.
+
+Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com>
+
+ * h8300.h: Reorder various #defines for readability.
+ (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
+ (BITOP): Accept additional (unused) argument. All callers changed.
+ (EBITOP): Likewise.
+ (O_LAST): Bump.
+ (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
+
+ * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
+ (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
+ (BITOP, EBITOP): Handle new H8/S addressing modes for
+ bit insns.
+ (UNOP3): Handle new shift/rotate insns on the H8/S.
+ (insns using exr): New instructions.
+ (tas, mac, ldmac, clrmac, ldm, stm): New instructions.
+
+Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (add.l): Undo Apr 5th change. The manual I had
+ was incorrect.
+
+Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (START): Remove.
+ (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w
+ and mov.l insns that can be relaxed.
+
+Tue Apr 30 18:30:58 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386.h: Remove Abs32 from lcall.
+
+Mon Apr 22 17:09:23 1996 Doug Evans <dje@blues.cygnus.com>
+
+ * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
+ (SLCPOP): New macro.
+ Mark X,Y opcode letters as in use.
+
+Thu Apr 11 17:28:18 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * sparc.h (F_FLOAT, F_FBR): Define.
+
+Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com)
+
+ * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV
+ from all insns.
+ (ABS8SRC,ABS8DST): Add ABS8MEM.
+ (add.l): Fix reg+reg variant.
+ (eepmov.w): Renamed from eepmovw.
+ (ldc,stc): Fix many cases.
+
+Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
+
+Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (O): Mark operand letter as in use.
+
+Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
+ Mark operand letters uU as in use.
+
+Mon Feb 19 01:59:08 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
+ (sparc_opcode_arch): Delete member `conflicts'. Add `supported'.
+ (SPARC_OPCODE_SUPPORTED): New macro.
+ (SPARC_OPCODE_CONFLICT_P): Rewrite.
+ (F_NOTV9): Delete.
+
+Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com)
+
+ * sparc.h (sparc_opcode_lookup_arch) Make return type in
+ declaration consistent with return type in definition.
+
+Wed Feb 14 18:14:11 1996 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h (i386_optab): Remove Data32 from pushf and popf.
+
+Thu Feb 8 14:27:21 1996 James Carlson <carlson@xylogics.com>
+
+ * i386.h (i386_regtab): Add 80486 test registers.
+
+Mon Feb 5 18:35:46 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i960.h (I_HX): Define.
+ (i960_opcodes): Add HX instruction.
+
+Mon Jan 29 12:43:39 1996 Ken Raeburn <raeburn@cygnus.com>
+
+ * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
+ and fclex.
+
+Wed Jan 24 22:36:59 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
+ (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
+ (bfd_* defines): Delete.
+ (sparc_opcode_archs): Replaces architecture_pname.
+ (sparc_opcode_lookup_arch): Declare.
+ (NUMOPCODES): Delete.
+
+Mon Jan 22 08:24:32 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (enum sparc_architecture): Add v9a.
+ (ARCHITECTURES_CONFLICT_P): Update.
+
+Thu Dec 28 13:27:53 1995 John Hassey <hassey@rtp.dg.com>
+
+ * i386.h: Added Pentium Pro instructions.
+
+Thu Nov 2 22:59:22 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k.h: Document new 'W' operand place.
+
+Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h: Add lci and syncdma instructions.
+
+Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
+
+ * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
+ instructions.
+
+Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com>
+
+ * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
+ assembler's -mcom and -many switches.
+
+Wed Oct 11 16:56:33 1995 Ken Raeburn <raeburn@cygnus.com>
+
+ * i386.h: Fix cmpxchg8b extension opcode description.
+
+Thu Oct 5 18:03:36 1995 Ken Raeburn <raeburn@cygnus.com>
+
+ * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
+ and register cr4.
+
+Tue Sep 19 15:26:43 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k.h: Change comment: split type P into types 0, 1 and 2.
+
+Wed Aug 30 13:50:55 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc.h (sparc_{encode,decode}_prefetch): Declare.
+
+Tue Aug 29 15:34:58 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
+
+Wed Aug 2 18:32:19 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68kmri.h: Remove.
+
+ * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
+ declarations. Remove F_ALIAS and flag field of struct
+ m68k_opcode. Change arch field of struct m68k_opcode to unsigned
+ int. Make name and args fields of struct m68k_opcode const.
+
+Wed Aug 2 08:16:46 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc.h (F_NOTV9): Define.
+
+Tue Jul 11 14:20:42 1995 Jeff Spiegel <jeffs@lsil.com>
+
+ * mips.h (INSN_4010): Define.
+
+Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
+
+ * m68k.h (TBL1): Reverse sense of "round" argument in result.
+
+ Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>:
+ * m68k.h: Fix argument descriptions of coprocessor
+ instructions to allow only alterable operands where appropriate.
+ [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
+ (m68k_opcode_aliases): Add more aliases.
+
+start-sanitize-arc
+Sat Apr 29 23:17:03 1995 Doug Evans <dje@chestnut.cygnus.com>
+
+ * arc.h (struct arc_opcode): New flag value ARC_OPCODE_COND_BRANCH.
+ (ARC_DELAY_{NONE,NORMAL,JUMP): Define delay slot types.
+end-sanitize-arc
+
+Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
+
+ * m68k.h: Added explcitly short-sized conditional branches, and a
+ bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
+ svr4-based configurations.
+
+start-sanitize-arc
+Wed Apr 12 08:54:32 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * arc.h (struct arc_opcode): New members next_asm, next_dis.
+ (ARC_HASH_OPCODE, ARC_HASH_ICODE): Define.
+ (ARC_OPCODE_NEXT_ASM, ARC_OPCODE_NEXT_DIS): Define.
+ (arc_opcode_lookup_asm, arc_opcode_lookup_dis): Add prototypes.
+
+Thu Apr 6 20:36:55 1995 Doug Evans <dje@chestnut.cygnus.com>
+
+ * arc.h (arc_get_opcode_mach): Define prototype.
+end-sanitize-arc
+
+Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
+
+ Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu>
+ * i386.h: added missing Data16/Data32 flags to a few instructions.
+
+Wed Mar 8 15:19:53 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips.h (OP_MASK_FR, OP_SH_FR): Define.
+ (OP_MASK_BCC, OP_SH_BCC): Define.
+ (OP_MASK_PREFX, OP_SH_PREFX): Define.
+ (OP_MASK_CCC, OP_SH_CCC): Define.
+ (INSN_READ_FPR_R): Define.
+ (INSN_RFE): Delete.
+
+Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
+
+ * m68k.h (enum m68k_architecture): Deleted.
+ (struct m68k_opcode_alias): New type.
+ (m68k_opcodes): Now const. Deleted opcode aliases with exactly
+ matching constraints, values and flags. As a side effect of this,
+ the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
+ as I know were never used, now may need re-examining.
+ (numopcodes): Now const.
+ (m68k_opcode_aliases, numaliases): New variables.
+ (endop): Deleted.
+ [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
+ m68k_opcode_aliases; update declaration of m68k_opcodes.
+
+start-sanitize-arc
+Tue Mar 7 21:03:26 1995 Doug Evans <dje@chestnut.cygnus.com>
+
+ * arc.h (ARC_MACH_BIG): Define.
+ (ARC_MACH_MASK): Update.
+ (ARC_MACH_CPU_MASK): Define.
+ (ARC_OPCODE_CPU, ARC_OPVAL_CPU, ARC_HAVE_CPU): Likewise.
+end-sanitize-arc
+
+Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu)
+
+ * hppa.h (delay_type): Delete unused enumeration.
+ (pa_opcode): Replace unused delayed field with an architecture
+ field.
+ (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
+
+Fri Mar 3 16:10:24 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips.h (INSN_ISA4): Define.
+
+Fri Feb 24 19:13:37 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips.h (M_DLA_AB, M_DLI): Define.
+
+Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu)
+
+ * hppa.h (fstwx): Fix single-bit error.
+
+Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
+
+start-sanitize-arc
+Mon Feb 13 11:05:00 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * arc.h (ARC_OPERAND_LIMM): New flag.
+ (ARC_OPERAND_ADDRESS): Likewise.
+
+Thu Feb 9 18:55:59 1995 Doug Evans <dje@canuck.cygnus.com>
+
+ * arc.h (ARC_MACH_{BASE,HOST,GRAPHICS,AUDIO}): Define.
+ (ARC_MACH_MASK, ARC_OPCODE_MACH, ARC_OPVAL_MACH): Define.
+ (ARC_HAVE_MULT_SHIFT): Delete.
+ (ARC_HAVE_MACH): Define.
+ (struct arc_opcode): New field `flags'.
+ (struct arc_operand_value): Ditto.
+ (arc_opcode_supported): New function.
+ (arc_opval_supported): Ditto.
+end-sanitize-arc
+
+Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * i386.h: added cpuid instruction , and dr[0-7] aliases for the
+ debug registers. From Charles Hannum (mycroft@netbsd.org).
+
Mon Feb 6 03:31:54 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit
Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
- * i960.h (I_CX2): New instruction category.
- start-sanitize-i960xl
- It includes instructions available on Cx and XL processors.
- (I_XL): New instruction category, for XL-only instructions.
- end-sanitize-i960xl
- (i960_opcodes): Put eshro and sysctl in I_CX2 category.
- start-sanitize-i960xl
- Added i960XL-only instructions, in I_XL category.
- end-sanitize-i960xl
+ * i960.h (I_CX2): New instruction category. It includes
+ instructions available on Cx and Jx processors.
+ (I_JX): New instruction category, for JX-only instructions.
+ (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added
+ Jx-only instructions, in I_JX category.
Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
projects / deliverable / binutils-gdb.git / blobdiff