+2000-12-01 Chris Demetriou <cgd@sibyte.com>
+
+ mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+ OP_*_SYSCALL definitions.
+ (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+ 19 bit wait codes.
+ (MIPS operand specifier comments): Remove 'm', add 'U' and
+ 'J', and update the meaning of 'B' so that it's more general.
+
+ * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+ INSN_ISA5): Renumber, redefine to mean the ISA at which the
+ instruction was added.
+ (INSN_ISA32): New constant.
+ (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+ Renumber to avoid new and/or renumbered INSN_* constants.
+ (INSN_MIPS32): Delete.
+ (ISA_UNKNOWN): New constant to indicate unknown ISA.
+ (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+ ISA_MIPS32): New constants, defined to be the mask of INSN_*
+ constants available at that ISA level.
+ (CPU_UNKNOWN): New constant to indicate unknown CPU.
+ (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+ define it with a unique value.
+ (OPCODE_IS_MEMBER): Update for new ISA membership-related
+ constant meanings.
+
+ * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+ definitions.
+
+2000-10-20 Jakub Jelinek <jakub@redhat.com>
+
+ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
+ Note that '3' is used for siam operand.
+
+2000-09-22 Jim Wilson <wilson@cygnus.com>
+
+ * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
+
+2000-09-13 Anders Norlander <anorland@acc.umu.se>
+
+ * mips.h: Use defines instead of hard-coded processor numbers.
+ (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
+ CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
+ CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
+ CPU_4KC, CPU_4KM, CPU_4KP): Define..
+ (OPCODE_IS_MEMBER): Use new defines.
+ (OP_MASK_SEL, OP_SH_SEL): Define.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define.
+ Add 'P' to used characters.
+ Use 'H' for coprocessor select field.
+ Use 'm' for 20 bit breakpoint code.
+ Document new arg characters and add to used characters.
+ (INSN_MIPS32): New define for MIPS32 extensions.
+ (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+
+2000-09-05 Alan Modra <alan@linuxcare.com.au>
+
+ * hppa.h: Mention cz completer.
+
+2000-08-16 Jim Wilson <wilson@cygnus.com>
+
+ * ia64.h (IA64_OPCODE_POSTINC): New.
+
2000-08-15 H.J. Lu <hjl@gnu.org>
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the