Add Intel Itanium Series 9500 support

[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4b8d3002c1bb8bceecb84b293388639a07ff900d..ce5c71de0755112be5bd0b457d40e56cdc8c657a 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,47 @@
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+       * ia64.h (ia64_opnd): Add new operand types.
+
+2012-08-21  David S. Miller  <davem@davemloft.net>
+
+       * sparc.h (F3F4): New macro.
+
+2012-08-13  Ian Bolton  <ian.bolton@arm.com>
+           Laurent Desnogues  <laurent.desnogues@arm.com>
+           Jim MacArthur  <jim.macarthur@arm.com>
+           Marcus Shawcroft  <marcus.shawcroft@arm.com>
+           Nigel Stephens  <nigel.stephens@arm.com>
+           Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+           Richard Earnshaw  <rearnsha@arm.com>
+           Sofiane Naci  <sofiane.naci@arm.com>
+           Tejas Belagod  <tejas.belagod@arm.com>
+           Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64.h: New file.
+
+2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips.h (mips_opcode): Add the exclusions field.
+       (OPCODE_IS_MEMBER): Remove macro.
+       (cpu_is_member): New inline function.
+       (opcode_is_member): Likewise.
+
+2012-07-31  Chao-Ying Fu  <fu@mips.com>
+           Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips.h: Document microMIPS DSP ASE usage.
+       (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+       microMIPS DSP ASE support.
+       (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+       (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+       (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+       (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+       (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+       (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+       (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+
 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * mips.h: Fix a typo in description.
@@ -70,7 +114,7 @@
        (XRELEASE_PREFIX_OPCODE): Likewise.
 
 2011-12-08  Andrew Pinski  <apinski@cavium.com>
-            Adam Nemet  <anemet@caviumnetworks.com>
+           Adam Nemet  <anemet@caviumnetworks.com>
 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
        (INSN_OCTEON2): New macro.
@@ -101,7 +145,7 @@
        F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 
 2011-08-09  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
 
        * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
@@ -147,7 +191,7 @@
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 
 2011-07-24  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
 
        * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
        (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
@@ -710,7 +754,7 @@
 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 
        * mips.h: Define CPU_R14000, CPU_R16000.
-        (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+       (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 
 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 
@@ -949,9 +993,9 @@
        * i386.h: Replace CpuMNI with CpuSSSE3.
 
 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
-            Joseph Myers  <joseph@codesourcery.com>
-            Ian Lance Taylor  <ian@wasabisystems.com>
-            Ben Elliston  <bje@wasabisystems.com>
+           Joseph Myers  <joseph@codesourcery.com>
+           Ian Lance Taylor  <ian@wasabisystems.com>
+           Ben Elliston  <bje@wasabisystems.com>
 
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 
@@ -994,18 +1038,18 @@
        * m68k.h (mcf_mask): Define.
 
 2006-05-05  Thiemo Seufer  <ths@mips.com>
-            David Ung  <davidu@mips.com>
+           David Ung  <davidu@mips.com>
 
        * mips.h (enum): Add macro M_CACHE_AB.
 
 2006-05-04  Thiemo Seufer  <ths@mips.com>
-            Nigel Stephens  <nigel@mips.com>
+           Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>
 
        * mips.h: Add INSN_SMARTMIPS define.
 
 2006-04-30  Thiemo Seufer  <ths@mips.com>
-            David Ung  <davidu@mips.com>
+           David Ung  <davidu@mips.com>
 
        * mips.h: Defines udi bits and masks.  Add description of
        characters which may appear in the args field of udi