+2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc.h (sparc_opcode): new field `hwcaps2'.
+ (HWCAP2_FJATHPLUS): New define.
+ (HWCAP2_VIS3B): Likewise.
+ (HWCAP2_ADP): Likewise.
+ (HWCAP2_SPARC5): Likewise.
+ (HWCAP2_MWAIT): Likewise.
+ (HWCAP2_XMPMUL): Likewise.
+ (HWCAP2_XMONT): Likewise.
+ (HWCAP2_NSEC): Likewise.
+ (HWCAP2_FJATHHPC): Likewise.
+ (HWCAP2_FJDES): Likewise.
+ (HWCAP2_FJAES): Likewise.
+ Document the new operand kind `{', corresponding to the mcdper
+ ancillary state register.
+ Document the new operand kind }, which represents frsd floating
+ point registers (double precision) which must be the same than
+ frs1 in its containing instruction.
+
+2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * nds32.h: Add new opcode declaration.
+
+2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
+ OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
+ instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+ +I, +O, +R, +:, +\, +", +;
+ (mips_check_prev_operand): New struct.
+ (INSN2_FORBIDDEN_SLOT): New define.
+ (INSN_ISA32R6): New define.
+ (INSN_ISA64R6): New define.
+ (INSN_UPTO32R6): New define.
+ (INSN_UPTO64R6): New define.
+ (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
+ (ISA_MIPS32R6): New define.
+ (ISA_MIPS64R6): New define.
+ (CPU_MIPS32R6): New define.
+ (CPU_MIPS64R6): New define.
+ (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
+ (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
+ (aarch64_insn_class): Add lse_atomic.
+ (F_LSE_SZ): New field added.
+ (opcode_has_special_coder): Recognize F_LSE_SZ.
+
+2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
+ over to `+J'.
+
+2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
+ (INSN_LOAD_COPROC): New define.
+ (INSN_COPROC_MOVE_DELAY): Rename to...
+ (INSN_COPROC_MOVE): New define.
+
+2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
+ Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+ Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+ Soundararajan <Sounderarajan.D@atmel.com>
+
+ * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
+ (AVR_ISA_2xxxa): Define ISA without LPM.
+ (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
+ Add doc for contraint used in 16 bit lds/sts.
+ Adjust ISA group for icall, ijmp, pop and push.
+ Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
+
+2014-05-19 Nick Clifton <nickc@redhat.com>
+
+ * msp430.h (struct msp430_operand_s): Add vshift field.
+
+2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips.h (INSN_ISA_MASK): Updated.
+ (INSN_ISA32R3): New define.
+ (INSN_ISA32R5): New define.
+ (INSN_ISA64R3): New define.
+ (INSN_ISA64R5): New define.
+ (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
+ INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
+ (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
+ mips64r5.
+ (INSN_UPTO32R3): New define.
+ (INSN_UPTO32R5): New define.
+ (INSN_UPTO64R3): New define.
+ (INSN_UPTO64R5): New define.
+ (ISA_MIPS32R3): New define.
+ (ISA_MIPS32R5): New define.
+ (ISA_MIPS64R3): New define.
+ (ISA_MIPS64R5): New define.
+ (CPU_MIPS32R3): New define.
+ (CPU_MIPS32R5): New define.
+ (CPU_MIPS64R3): New define.
+ (CPU_MIPS64R5): New define.
+
+2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
+
+2014-04-22 Christian Svensson <blue@cmd.nu>
+
+ * or32.h: Delete.
+
+2014-03-05 Alan Modra <amodra@gmail.com>
+
+ Update copyright years.
+
+2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips.h: Updated description of +o, +u, +v and +w for MIPS and
+ microMIPS.
+
+2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+ Wei-Cheng Wang <cole945@gmail.com>
+
+ * nds32.h: New file for Andes NDS32.
+
+2013-12-07 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Remove +x file mode.
+
+2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_pstatefields): Change element type to
+ aarch64_sys_reg.
+
2013-11-18 Renlin Li <Renlin.Li@arm.com>
* arm.h (ARM_AEXT_V7VE): New define.
For older changes see ChangeLog-9103
\f
-Copyright (C) 2004-2012 Free Software Foundation, Inc.
+Copyright (C) 2004-2014 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff