Add support for V_4B so we can properly reject it.

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a597ebe0cbdb78b5abeb3268b53024d85de6b601..453b1771f02a9884652b44ec9c16ea5bbced1a83 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,9 @@ typedef uint32_t aarch64_insn;
 /* The following bitmasks control CPU features.  */
 #define AARCH64_FEATURE_SHA2   0x200000000ULL  /* SHA2 instructions.  */
 #define AARCH64_FEATURE_AES    0x800000000ULL  /* AES instructions.  */
+#define AARCH64_FEATURE_V8_4   0x000000800ULL  /* ARMv8.4 processors.  */
+#define AARCH64_FEATURE_SM4    0x100000000ULL  /* SM3 & SM4 instructions.  */
+#define AARCH64_FEATURE_SHA3   0x400000000ULL  /* SHA3 instructions.  */
 #define AARCH64_FEATURE_V8     0x00000001      /* All processors.  */
 #define AARCH64_FEATURE_V8_2   0x00000020      /* ARMv8.2 processors.  */
 #define AARCH64_FEATURE_V8_3   0x00000040      /* ARMv8.3 processors.  */
@@ -58,6 +61,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_RCPC   0x20000000      /* RCPC instructions.  */
 #define AARCH64_FEATURE_COMPNUM        0x40000000      /* Complex # instructions.  */
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
+#define AARCH64_FEATURE_F16_FML        0x1000000000ULL /* v8.2 FP16FML ins.  */
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8                AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -77,6 +81,10 @@ typedef uint32_t aarch64_insn;
                                                 AARCH64_FEATURE_V8_3   \
                                                 | AARCH64_FEATURE_RCPC \
                                                 | AARCH64_FEATURE_COMPNUM)
+#define AARCH64_ARCH_V8_4      AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
+                                                AARCH64_FEATURE_V8_4   \
+                                                | AARCH64_FEATURE_DOTPROD \
+                                                | AARCH64_FEATURE_F16_FML)
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
@@ -161,6 +169,7 @@ enum aarch64_opnd
   AARCH64_OPND_Sn,     /* AdvSIMD Scalar Sn.  */
   AARCH64_OPND_Sm,     /* AdvSIMD Scalar Sm.  */
 
+  AARCH64_OPND_Va,     /* AdvSIMD Vector Va.  */
   AARCH64_OPND_Vd,     /* AdvSIMD Vector Vd.  */
   AARCH64_OPND_Vn,     /* AdvSIMD Vector Vn.  */
   AARCH64_OPND_Vm,     /* AdvSIMD Vector Vm.  */
@@ -179,6 +188,7 @@ enum aarch64_opnd
   AARCH64_OPND_CRm,    /* Co-processor register in CRm field.  */
 
   AARCH64_OPND_IDX,    /* AdvSIMD EXT index operand.  */
+  AARCH64_OPND_MASK,   /* AdvSIMD EXT index operand.  */
   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
@@ -193,6 +203,7 @@ enum aarch64_opnd
   AARCH64_OPND_IMMS,   /* Immediate #<imms> in e.g. BFM.  */
   AARCH64_OPND_WIDTH,  /* Immediate #<width> in e.g. BFI.  */
   AARCH64_OPND_IMM,    /* Immediate.  */
+  AARCH64_OPND_IMM_2,  /* Immediate.  */
   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
   AARCH64_OPND_UIMM4,  /* Unsigned 4-bit immediate in the CRm field.  */
@@ -236,6 +247,7 @@ enum aarch64_opnd
   AARCH64_OPND_ADDR_SIMM10,    /* Address of signed 10-bit immediate.  */
   AARCH64_OPND_ADDR_UIMM12,    /* Address of unsigned 12-bit immediate.  */
   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
+  AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
   AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed.  */
 
   AARCH64_OPND_SYSREG,         /* System register operand.  */
@@ -348,6 +360,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_ZnxN,       /* SVE vector register list in Zn.  */
   AARCH64_OPND_SVE_Zt,         /* SVE vector register in Zt.  */
   AARCH64_OPND_SVE_ZtxN,       /* SVE vector register list in Zt.  */
+  AARCH64_OPND_SM3_IMM2,       /* SM3 encodes lane in bits [13, 14].  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an
@@ -390,6 +403,7 @@ enum aarch64_opnd_qualifier
      a use is only for the ease of operand encoding/decoding and qualifier
      sequence matching; such a use should not be applied widely; use the value
      constraint qualifiers for immediate operands wherever possible.  */
+  AARCH64_OPND_QLF_V_4B,
   AARCH64_OPND_QLF_V_8B,
   AARCH64_OPND_QLF_V_16B,
   AARCH64_OPND_QLF_V_2H,
@@ -510,6 +524,8 @@ enum aarch64_insn_class
   sve_size_hsd,
   sve_size_sd,
   testbranch,
+  cryptosm3,
+  cryptosm4,
   dotproduct,
 };