[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d1d366b439c8de980ce82ff0027552494d568bd9..4cda1e079e03a70a808a6c03e36dcfe221751919 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -63,6 +63,8 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML        0x1000000000ULL /* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5   0x2000000000ULL /* ARMv8.5 processors.  */
+#define AARCH64_FEATURE_V8_6   0x00000002      /* ARMv8.6 processors.  */
+#define AARCH64_FEATURE_BFLOAT16       0x00000004      /* Bfloat16 insns.  */
 
 /* Flag Manipulation insns.  */
 #define AARCH64_FEATURE_FLAGMANIP      0x4000000000ULL
@@ -129,7 +131,9 @@ typedef uint32_t aarch64_insn;
                                                 | AARCH64_FEATURE_SCXTNUM \
                                                 | AARCH64_FEATURE_ID_PFR2 \
                                                 | AARCH64_FEATURE_SSBS)
-
+#define AARCH64_ARCH_V8_6      AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
+                                                AARCH64_FEATURE_V8_6   \
+                                                | AARCH64_FEATURE_BFLOAT16)
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
@@ -392,6 +396,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_Rn_SP,      /* Integer Rn or SP, alt. SVE position.  */
   AARCH64_OPND_SVE_SHLIMM_PRED,          /* SVE shift left amount (predicated).  */
   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
+  AARCH64_OPND_SVE_SHLIMM_UNPRED_22,   /* SVE 3 bit shift left unpred.  */
   AARCH64_OPND_SVE_SHRIMM_PRED,          /* SVE shift right amount (predicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,   /* SVE 3 bit shift right unpred.  */
@@ -415,6 +420,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_Zm3_INDEX,  /* z0-z7[0-3] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
+  AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
   AARCH64_OPND_SVE_Zm4_INDEX,  /* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,         /* SVE vector register in Zn.  */
   AARCH64_OPND_SVE_Zn_INDEX,   /* Indexed SVE vector register, for DUP.  */
@@ -458,11 +464,13 @@ enum aarch64_opnd_qualifier
   AARCH64_OPND_QLF_S_S,
   AARCH64_OPND_QLF_S_D,
   AARCH64_OPND_QLF_S_Q,
-  /* This type qualifier has a special meaning in that it means that 4 x 1 byte
-     are selected by the instruction.  Other than that it has no difference
-     with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
-     reasons and is an exception from normal AArch64 disassembly scheme.  */
+  /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
+     or 2 x 2 byte are selected by the instruction.  Other than that they have
+     no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
+     for syntactical reasons and is an exception from normal AArch64
+     disassembly scheme.  */
   AARCH64_OPND_QLF_S_4B,
+  AARCH64_OPND_QLF_S_2H,
 
   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
      register list; indicating register shape.
@@ -597,13 +605,15 @@ enum aarch64_insn_class
   sve_size_sd,
   sve_size_bh,
   sve_size_sd2,
-  sve_size_013,
+  sve_size_13,
   sve_shift_tsz_hsd,
   sve_shift_tsz_bhsd,
+  sve_size_tsz_bhs,
   testbranch,
   cryptosm3,
   cryptosm4,
   dotproduct,
+  bfloat16,
 };
 
 /* Opcode enumerators.  */