RISC-V: Fix the error when building RISC-V linux native gdbserver.

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4cda1e079e03a70a808a6c03e36dcfe221751919..817ca1e674effd246f1b76cdc88d84ca9a507970 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1,6 +1,6 @@
 /* AArch64 assembler/disassembler support.
 
-   Copyright (C) 2009-2019 Free Software Foundation, Inc.
+   Copyright (C) 2009-2020 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of GNU Binutils.
@@ -45,7 +45,6 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_V8     0x00000001      /* All processors.  */
 #define AARCH64_FEATURE_V8_2   0x00000020      /* ARMv8.2 processors.  */
 #define AARCH64_FEATURE_V8_3   0x00000040      /* ARMv8.3 processors.  */
-#define AARCH64_FEATURE_CRYPTO 0x00010000      /* Crypto instructions.  */
 #define AARCH64_FEATURE_FP     0x00020000      /* FP instructions.  */
 #define AARCH64_FEATURE_SIMD   0x00040000      /* SIMD instructions.  */
 #define AARCH64_FEATURE_CRC    0x00080000      /* CRC instructions.  */
@@ -91,6 +90,11 @@ typedef uint32_t aarch64_insn;
 /* Transactional Memory Extension.  */
 #define AARCH64_FEATURE_TME            0x2000000000000ULL
 
+/* Matrix Multiply instructions */
+#define AARCH64_FEATURE_I8MM           0x10000000000000ULL
+#define AARCH64_FEATURE_F32MM          0x20000000000000ULL
+#define AARCH64_FEATURE_F64MM          0x40000000000000ULL
+
 /* SVE2 instructions.  */
 #define AARCH64_FEATURE_SVE2           0x000000010
 #define AARCH64_FEATURE_SVE2_AES               0x000000080
@@ -98,6 +102,9 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SVE2_SM4               0x000000200
 #define AARCH64_FEATURE_SVE2_SHA3      0x000000400
 
+/* Crypto instructions are the combination of AES and SHA2.  */
+#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
+
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8                AARCH64_FEATURE (AARCH64_FEATURE_V8, \
                                                 AARCH64_FEATURE_FP  \
@@ -133,7 +140,8 @@ typedef uint32_t aarch64_insn;
                                                 | AARCH64_FEATURE_SSBS)
 #define AARCH64_ARCH_V8_6      AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
                                                 AARCH64_FEATURE_V8_6   \
-                                                | AARCH64_FEATURE_BFLOAT16)
+                                                | AARCH64_FEATURE_BFLOAT16 \
+                                                | AARCH64_FEATURE_I8MM)
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
@@ -264,6 +272,7 @@ enum aarch64_opnd
   AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg.  */
   AARCH64_OPND_BIT_NUM,        /* Immediate.  */
   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
+  AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
   AARCH64_OPND_SIMM5,  /* 5-bit signed immediate in the imm5 field.  */
   AARCH64_OPND_NZCV,   /* Flag bit specifier giving an alternative value for
@@ -322,6 +331,7 @@ enum aarch64_opnd
   AARCH64_OPND_BTI_TARGET,     /* BTI {<target>}.  */
 
   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
+  AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
@@ -520,6 +530,7 @@ enum aarch64_opnd_qualifier
 
 enum aarch64_insn_class
 {
+  aarch64_misc,
   addsub_carry,
   addsub_ext,
   addsub_imm,