[binutils][aarch64] New sve_size_sd2 iclass.

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a7a7459c5fb5a928399792ca38ed204683923f59..874999303985a8af3bbf44fe2b41e7a967fa0221 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -337,6 +337,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
+  AARCH64_OPND_SVE_ADDR_ZX,        /* SVE [Zn.<T>{, <Xm>}].  */
   AARCH64_OPND_SVE_ADDR_RZ,        /* SVE [<Xn|SP>, Zm.D].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
@@ -412,6 +413,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_Zm_16,      /* SVE vector register in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_INDEX,  /* z0-z7[0-3] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
+  AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
   AARCH64_OPND_SVE_Zm4_INDEX,  /* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,         /* SVE vector register in Zn.  */
   AARCH64_OPND_SVE_Zn_INDEX,   /* Indexed SVE vector register, for DUP.  */
@@ -592,6 +594,7 @@ enum aarch64_insn_class
   sve_size_hsd,
   sve_size_hsd2,
   sve_size_sd,
+  sve_size_sd2,
   testbranch,
   cryptosm3,
   cryptosm4,