[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions

[deliverable/binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 10bf097ff39c56ca305141cde4ae2471fe129283..b4987ded4508e5f5fcce3cbfbff1d05287081cf7 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -62,6 +62,20 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_COMPNUM        0x40000000      /* Complex # instructions.  */
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML        0x1000000000ULL /* v8.2 FP16FML ins.  */
+#define AARCH64_FEATURE_V8_5   0x2000000000ULL /* ARMv8.5 processors.  */
+
+/* Flag Manipulation insns.  */
+#define AARCH64_FEATURE_FLAGMANIP      0x4000000000ULL
+/* FRINT[32,64][Z,X] insns.  */
+#define AARCH64_FEATURE_FRINTTS                0x8000000000ULL
+/* SB instruction.  */
+#define AARCH64_FEATURE_SB             0x10000000000ULL
+/* Execution and Data Prediction Restriction instructions.  */
+#define AARCH64_FEATURE_PREDRES                0x20000000000ULL
+/* DC CVADP.  */
+#define AARCH64_FEATURE_CVADP          0x40000000000ULL
+/* Random Number instructions.  */
+#define AARCH64_FEATURE_RNG            0x80000000000ULL
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8                AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -85,6 +99,14 @@ typedef uint32_t aarch64_insn;
                                                 AARCH64_FEATURE_V8_4   \
                                                 | AARCH64_FEATURE_DOTPROD \
                                                 | AARCH64_FEATURE_F16_FML)
+#define AARCH64_ARCH_V8_5      AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
+                                                AARCH64_FEATURE_V8_5   \
+                                                | AARCH64_FEATURE_FLAGMANIP \
+                                                | AARCH64_FEATURE_FRINTTS \
+                                                | AARCH64_FEATURE_SB   \
+                                                | AARCH64_FEATURE_PREDRES \
+                                                | AARCH64_FEATURE_CVADP)
+
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
@@ -258,6 +280,7 @@ enum aarch64_opnd
   AARCH64_OPND_SYSREG_DC,      /* System register <dc_op> operand.  */
   AARCH64_OPND_SYSREG_IC,      /* System register <ic_op> operand.  */
   AARCH64_OPND_SYSREG_TLBI,    /* System register <tlbi_op> operand.  */
+  AARCH64_OPND_SYSREG_SR,      /* System register RCTX operand.  */
   AARCH64_OPND_BARRIER,                /* Barrier operand.  */
   AARCH64_OPND_BARRIER_ISB,    /* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,          /* Prefetch operation.  */
@@ -641,6 +664,17 @@ enum aarch64_op
   OP_TOTAL_NUM,                /* Pseudo.  */
 };
 
+/* Error types.  */
+enum err_type
+{
+  ERR_OK,
+  ERR_UND,
+  ERR_UNP,
+  ERR_NYI,
+  ERR_VFI,
+  ERR_NR_ENTRIES
+};
+
 /* Maximum number of operands an instruction can have.  */
 #define AARCH64_MAX_OPND_NUM 6
 /* Maximum number of qualifier sequences an instruction can have.  */
@@ -717,7 +751,9 @@ struct aarch64_opcode
   unsigned char tied_operand;
 
   /* If non-NULL, a function to verify that a given instruction is valid.  */
-  bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
+  enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
+                             bfd_vma, bfd_boolean, aarch64_operand_error *,
+                             struct aarch64_instr_sequence *);
 };
 
 typedef struct aarch64_opcode aarch64_opcode;
@@ -888,6 +924,7 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 
 /* Shift/extending operator kinds.
    N.B. order is important; keep aarch64_operand_modifiers synced.  */
@@ -1053,7 +1090,6 @@ struct aarch64_inst
   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 };
 
-typedef struct aarch64_inst aarch64_inst;
 \f
 /* Diagnosis related declaration and interface.  */
 
@@ -1178,6 +1214,9 @@ extern aarch64_opnd_qualifier_t
 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
                                const aarch64_opnd_qualifier_t, int);
 
+extern bfd_boolean
+aarch64_is_destructive_by_operands (const aarch64_opcode *);
+
 extern int
 aarch64_num_of_operands (const aarch64_opcode *);
 
@@ -1187,9 +1226,12 @@ aarch64_stack_pointer_p (const aarch64_opnd_info *);
 extern int
 aarch64_zero_register_p (const aarch64_opnd_info *);
 
-extern int
+extern enum err_type
 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
-                    aarch64_operand_error *errors);
+                    aarch64_operand_error *);
+
+extern void
+init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
 
 /* Given an operand qualifier, return the expected data element size
    of a qualified operand.  */