gas/

[deliverable/binutils-gdb.git] / include / opcode / i386.h

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 27e73fd66bcec558a71717acc678c0cd1ee649c7..cb3a99a4e6fd41c61b7c3647dcda06b601ad0985 100644 (file)
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1,6 +1,7 @@
 /* opcode/i386.h -- Intel 80386 opcode table
-   Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
-   Free Software Foundation.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000, 2001
+   Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
 
@@ -61,6 +62,7 @@ static const template i386_optab[] = {
 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
+#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
@@ -119,9 +121,9 @@ static const template i386_optab[] = {
 {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg32|WordMem, Reg64, 0} },
 /* Intel Syntax next 5 insns */
 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize,       { Reg16|ShortMem, Reg32, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                  { Reg16|ShortMem, Reg32, 0} },
 {"movsx",  2, 0x0fbe, X, Cpu64,  b_Suf|Modrm|Rex64,            { Reg8|ByteMem, Reg64, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|Rex64,            { Reg16|ShortMem, Reg64, 0} },
 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,            { Reg32|WordMem, Reg64, 0} },
 
 /* Move with zero extend.  */
@@ -133,11 +135,11 @@ static const template i386_optab[] = {
 {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg16|ShortMem, Reg64, 0} },
 /* Intel Syntax next 4 insns */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize,       { Reg16|ShortMem, Reg32, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                  { Reg16|ShortMem, Reg32, 0} },
 /* These instructions are not particulary usefull, since the zero extend
    32->64 is implicit, but we can encode them.  */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64,            { Reg8|ByteMem, Reg64, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64,            { Reg16|ShortMem, Reg64, 0} },
 
 /* Push instructions.  */
 {"push",   1,  0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
@@ -147,14 +149,14 @@ static const template i386_optab[] = {
 {"push",   1,  0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
 {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"push",   1,  0x50, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } },
-{"push",   1,  0xff, 6, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } },
-{"push",   1,  0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
-{"push",   1,  0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} },
-{"push",   1,  0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"push",   1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"push",   1,  0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
+{"push",   1,  0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
+{"push",   1,  0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
+{"push",   1,  0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
+{"push",   1,  0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"push",   1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
-{"pusha",  0,  0x60, X, Cpu186|Cpu64, wl_Suf|DefaultSize,      { 0, 0, 0 } },
+{"pusha",  0,  0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0 } },
 
 /* Pop instructions.  */
 {"pop",           1,   0x58, X, CpuNo64,        wl_Suf|ShortForm|DefaultSize,  { WordReg, 0, 0 } },
@@ -163,10 +165,10 @@ static const template i386_optab[] = {
 {"pop",           1,   0x07, X, CpuNo64,        wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
 {"pop",           1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"pop",           1,   0x58, X, Cpu64,  q_Suf|ShortForm|DefaultSize|NoRex64,   { Reg64, 0, 0 } },
-{"pop",           1,   0x8f, 0, Cpu64,  q_Suf|Modrm|DefaultSize|NoRex64,       { Reg64|WordMem, 0, 0 } },
-{"pop",           1,   0x07, X, Cpu64,  q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"pop",           1, 0x0fa1, X, Cpu64,  q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"pop",           1,   0x58, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { WordReg, 0, 0 } },
+{"pop",           1,   0x8f, 0, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,      { WordReg|WordMem, 0, 0 } },
+{"pop",           1,   0x07, X, Cpu64,  wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"pop",           1, 0x0fa1, X, Cpu64,  wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
 {"popa",   0,  0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },
 
@@ -175,20 +177,20 @@ static const template i386_optab[] = {
  
    In the 64bit code, xchg eax, eax is reused for new nop instruction.
  */
-{"xchg",   2,  0x90, X, CpuNo64, wl_Suf|ShortForm,     { WordReg, Acc, 0 } },
-{"xchg",   2,  0x90, X, CpuNo64, wl_Suf|ShortForm,     { Acc, WordReg, 0 } },
+{"xchg",   2,  0x90, X, 0,      wlq_Suf|ShortForm,     { WordReg, Acc, 0 } },
+{"xchg",   2,  0x90, X, 0,      wlq_Suf|ShortForm,     { Acc, WordReg, 0 } },
 {"xchg",   2,  0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0 } },
 {"xchg",   2,  0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Reg, 0 } },
 
 /* In/out from ports.  */
-{"in",    2,   0xe4, X, 0,      bwlq_Suf|W,            { Imm8, Acc, 0 } },
-{"in",    2,   0xec, X, 0,      bwlq_Suf|W,            { InOutPortReg, Acc, 0 } },
-{"in",    1,   0xe4, X, 0,      bwlq_Suf|W,            { Imm8, 0, 0 } },
-{"in",    1,   0xec, X, 0,      bwlq_Suf|W,            { InOutPortReg, 0, 0 } },
-{"out",           2,   0xe6, X, 0,      bwlq_Suf|W,            { Acc, Imm8, 0 } },
-{"out",           2,   0xee, X, 0,      bwlq_Suf|W,            { Acc, InOutPortReg, 0 } },
-{"out",           1,   0xe6, X, 0,      bwlq_Suf|W,            { Imm8, 0, 0 } },
-{"out",           1,   0xee, X, 0,      bwlq_Suf|W,            { InOutPortReg, 0, 0 } },
+{"in",    2,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, Acc, 0 } },
+{"in",    2,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, Acc, 0 } },
+{"in",    1,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
+{"in",    1,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
+{"out",           2,   0xe6, X, 0,      bwl_Suf|W,             { Acc, Imm8, 0 } },
+{"out",           2,   0xee, X, 0,      bwl_Suf|W,             { Acc, InOutPortReg, 0 } },
+{"out",           1,   0xe6, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
+{"out",           1,   0xee, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
 
 /* Load effective address.  */
 {"lea",           2, 0x8d,   X, 0,      wlq_Suf|Modrm,         { WordMem, WordReg, 0 } },
@@ -209,9 +211,9 @@ static const template i386_optab[] = {
 {"lahf",   0,  0x9f, X, CpuNo64,NoSuf,                 { 0, 0, 0} },
 {"sahf",   0,  0x9e, X, CpuNo64,NoSuf,                 { 0, 0, 0} },
 {"pushf",  0,  0x9c, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"pushf",  0,  0x9c, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"pushf",  0,  0x9c, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"popf",   0,  0x9d, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"popf",   0,  0x9d, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"popf",   0,  0x9d, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"stc",           0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"std",           0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"sti",           0,   0xfb, X, 0,      NoSuf,                 { 0, 0, 0} },
@@ -369,7 +371,8 @@ static const template i386_optab[] = {
 
 /* Control transfer instructions.  */
 {"call",   1,  0xe8, X, 0,      wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
-{"call",   1,  0xff, 2, 0,      wlq_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,  0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,  0xff, 2, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"call",   2,  0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
@@ -380,7 +383,8 @@ static const template i386_optab[] = {
 
 #define JUMP_PC_RELATIVE 0xeb
 {"jmp",           1,   0xeb, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
-{"jmp",           1,   0xff, 4, 0,      wlq_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",           1,   0xff, 4, CpuNo64, wl_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",           1,   0xff, 4, Cpu64,  wq_Suf|Modrm|NoRex64,  { WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"jmp",    2,  0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
@@ -389,8 +393,10 @@ static const template i386_optab[] = {
 {"ljmp",   1,  0xff, 5, CpuNo64,        wl_Suf|Modrm,          { WordMem|JumpAbsolute, 0, 0} },
 {"ljmp",   1,  0xff, 5, Cpu64,  q_Suf|Modrm|NoRex64,   { WordMem|JumpAbsolute, 0, 0} },
 
-{"ret",           0,   0xc3, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"ret",           1,   0xc2, X, 0,      wlq_Suf|DefaultSize,   { Imm16, 0, 0} },
+{"ret",           0,   0xc3, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
+{"ret",           1,   0xc2, X, CpuNo64,wlq_Suf|DefaultSize,   { Imm16, 0, 0} },
+{"ret",           0,   0xc3, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"ret",           1,   0xc2, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
 {"lret",   0,  0xcb, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
 {"lret",   1,  0xca, X, 0,      wlq_Suf|DefaultSize,   { Imm16, 0, 0} },
 {"enter",  2,  0xc8, X, Cpu186, wlq_Suf|DefaultSize,   { Imm16, Imm8, 0} },
@@ -429,18 +435,25 @@ static const template i386_optab[] = {
 {"jg",    1,   0x7f, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 
 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
-{"jcxz",   1,  0xe3, X, 0,      NoSuf|JumpByte|Size16, { Disp, 0, 0} },
-{"jecxz",  1,  0xe3, X, 0,      NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jcxz",  1,   0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
+{"jecxz",  1,  0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jecxz",  1,  0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jrcxz",  1,  0xe3, X, Cpu64,  NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
 
 /* The loop instructions also use the address size prefix to select
    %cx rather than %ecx for the loop count, so the `w' form of these
    instructions emit an address size prefix rather than a data size
    prefix.  */
-{"loop",   1,  0xe2, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopz",  1,  0xe1, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loope",  1,  0xe1, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopnz", 1,  0xe0, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopne", 1,  0xe0, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
+{"loop",   1,  0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loop",   1,  0xe2, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopz",  1,  0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopz",  1,  0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loope",  1,  0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loope",  1,  0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopnz", 1,  0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopnz", 1,  0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopne", 1,  0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopne", 1,  0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 
 /* Set byte on flag instructions.  */
 {"seto",   1, 0x0f90, 0, Cpu386, b_Suf|Modrm,          { Reg8|ByteMem, 0, 0} },
@@ -479,10 +492,10 @@ static const template i386_optab[] = {
 {"cmps",   2,  0xa6, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, AnyMem, 0} },
 {"scmp",   0,  0xa6, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 {"scmp",   2,  0xa6, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, AnyMem, 0} },
-{"ins",           0,   0x6c, X, Cpu186, bwlq_Suf|W|IsString,   { 0, 0, 0} },
-{"ins",           2,   0x6c, X, Cpu186, bwlq_Suf|W|IsString,   { InOutPortReg, AnyMem|EsSeg, 0} },
-{"outs",   0,  0x6e, X, Cpu186, bwlq_Suf|W|IsString,   { 0, 0, 0} },
-{"outs",   2,  0x6e, X, Cpu186, bwlq_Suf|W|IsString,   { AnyMem, InOutPortReg, 0} },
+{"ins",           0,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
+{"ins",           2,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { InOutPortReg, AnyMem|EsSeg, 0} },
+{"outs",   0,  0x6e, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
+{"outs",   2,  0x6e, X, Cpu186, bwl_Suf|W|IsString,    { AnyMem, InOutPortReg, 0} },
 {"lods",   0,  0xac, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 {"lods",   1,  0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, 0, 0} },
 {"lods",   2,  0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, Acc, 0} },
@@ -550,9 +563,12 @@ static const template i386_optab[] = {
 
 {"sgdt",   1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm,                { WordMem, 0, 0} },
 {"sidt",   1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm,                { WordMem, 0, 0} },
-{"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,                { WordReg|WordMem, 0, 0} },
-{"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,                { WordReg|WordMem, 0, 0} },
-{"str",           1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,                { WordReg|InvMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,                { WordReg|InvMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
+{"str",           1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
+{"str",           1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
 
 {"verr",   1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 {"verw",   1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
@@ -965,12 +981,16 @@ static const template i386_optab[] = {
 {"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,           { Reg32|LLongMem, RegXMM, 0 } },
 {"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,           { RegXMM, Reg32|LLongMem, 0 } },
 /* Real MMX instructions.  */
+{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,           { Reg64|LLongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,           { RegMMX, Reg64|LLongMem, 0 } },
+{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,           { Reg64|LLongMem, RegXMM, 0 } },
+{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,           { RegXMM, Reg64|LLongMem, 0 } },
+/* In the 64bit mode the short form mov immediate is redefined to have
+   64bit displacement value.  */
 {"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,           { RegMMX, RegMMX|LongMem, 0 } },
 {"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,           { RegXMM, RegXMM|LLongMem, 0 } },
-/* In the 64bit mode the short form mov immediate is redefined to have
-   64bit displacement value.  */
 {"movq",   2,  0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
 {"movq",   2,  0xc6, 0, Cpu64,  NoSuf|W|Modrm|Size64,  { Imm32S, Reg64|WordMem, 0 } },
 {"movq",   2,  0xb0, X, Cpu64,  NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
@@ -990,6 +1010,8 @@ static const template i386_optab[] = {
 {"paddw",    2, 0x660ffd,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddd",    2, 0x0ffe, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"paddd",    2, 0x660ffe,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddq",    2, 0x0fd4, X, CpuMMX, FP|Modrm,           { RegMMX|LLongMem, RegMMX, 0 } },
+{"paddq",    2, 0x660fd4,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddsb",   2, 0x0fec, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"paddsb",   2, 0x660fec,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"paddsw",   2, 0x0fed, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
@@ -1060,6 +1082,8 @@ static const template i386_optab[] = {
 {"psubw",    2, 0x660ff9,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubd",    2, 0x0ffa, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"psubd",    2, 0x660ffa,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubq",    2, 0x0ffb, X, CpuMMX, FP|Modrm,           { RegMMX|LLongMem, RegMMX, 0 } },
+{"psubq",    2, 0x660ffb,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubsb",   2, 0x0fe8, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
 {"psubsb",   2, 0x660fe8,X,CpuSSE2,FP|Modrm,           { RegXMM|LLongMem, RegXMM, 0 } },
 {"psubsw",   2, 0x0fe9, X, CpuMMX, FP|Modrm,           { RegMMX|LongMem, RegMMX, 0 } },
@@ -1110,10 +1134,10 @@ static const template i386_optab[] = {
 {"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegXMM, 0 } },
 {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, FP|Modrm,       { Reg32|WordMem, RegXMM, 0 } },
-{"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, Reg32, 0 } },
+{"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
+{"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
 {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, Reg32, 0 } },
+{"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,        { RegXMM|WordMem, Reg32|Reg64, 0 } },
 {"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm,       { WordMem, 0, 0 } },
@@ -1130,10 +1154,10 @@ static const template i386_optab[] = {
 {"movlhps",   2, 0x0f16,    X, CpuSSE, FP|Modrm,       { RegXMM|InvMem, RegXMM, 0 } },
 {"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,       { LLongMem, RegXMM, 0 } },
 {"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,       { RegXMM, LLongMem, 0 } },
-{"movmskps",  2, 0x0f50,    X, CpuSSE, FP|Modrm,       { RegXMM|InvMem, Reg32, 0 } },
+{"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,        { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm,       { RegXMM, LLongMem, 0 } },
 {"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm,       { RegMMX, LLongMem, 0 } },
-{"movntq",    2, 0x660fe7,  X, CpuSSE2,FP|Modrm,       { RegXMM, LLongMem, 0 } },
+{"movntdq",   2, 0x660fe7,  X, CpuSSE2,FP|Modrm,       { RegXMM, LLongMem, 0 } },
 {"movss",     2, 0xf30f10,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"movss",     2, 0xf30f11,  X, CpuSSE, FP|Modrm,       { RegXMM, RegXMM|WordMem, 0 } },
 {"movups",    2, 0x0f10,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1145,9 +1169,10 @@ static const template i386_optab[] = {
 {"pavgb",     2, 0x660fe0,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
-{"pextrw",    3, 0x0fc5,    X, CpuSSE, FP|Modrm,       { Imm8, RegMMX, Reg32|InvMem } },
-{"pextrw",    3, 0x660fc5,  X, CpuSSE2,FP|Modrm,       { Imm8, RegXMM, Reg32|InvMem } },
-{"pinsrw",    3, 0x0fc4,    X, CpuSSE, FP|Modrm,       { Imm8, Reg32|ShortMem, RegMMX } },
+{"pextrw",    3, 0x0fc5,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,        { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
+{"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,        { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
+{"pinsrw",    3, 0x0fc4,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,        { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
+{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
 {"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
 {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
@@ -1156,8 +1181,8 @@ static const template i386_optab[] = {
 {"pminsw",    2, 0x660fea,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
 {"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, FP|Modrm,       { RegMMX, Reg32|InvMem, 0 } },
-{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,FP|Modrm,       { RegXMM, Reg32|InvMem, 0 } },
+{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,        { RegMMX|InvMem, Reg32|Reg64, 0 } },
+{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,        { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
 {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm,       { LLongMem, 0, 0 } },
@@ -1167,7 +1192,6 @@ static const template i386_optab[] = {
 {"psadbw",    2, 0x0ff6,    X, CpuSSE, FP|Modrm,       { RegMMX|LLongMem, RegMMX, 0 } },
 {"psadbw",    2, 0x660ff6,  X, CpuSSE2,FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"pshufw",    3, 0x0f70,    X, CpuSSE, FP|Modrm,       { Imm8, RegMMX|LLongMem, RegMMX } },
-{"pshufw",    3, 0x660f70,  X, CpuSSE2,FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
 {"rcpps",     2, 0x0f53,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
 {"rcpss",     2, 0xf30f53,  X, CpuSSE, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
 {"rsqrtps",   2, 0x0f52,    X, CpuSSE, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1207,10 +1231,13 @@ static const template i386_optab[] = {
 {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
 {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
 {"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
+/* Intel mode string compare.  */
+{"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LongMem, RegXMM } },
 {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
 {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,      { RegMMX|LLongMem, RegXMM, 0 } },
-{"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, FP|Modrm,      { Reg32|LongMem, RegXMM, 0 } },
+{"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
 {"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
 {"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1223,8 +1250,11 @@ static const template i386_optab[] = {
 {"movhpd",    2, 0x660f17,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
 {"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,      { LLongMem, RegXMM, 0 } },
 {"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
-{"movmskpd",  2, 0x660f50,  X, CpuSSE2, FP|Modrm,      { RegXMM|InvMem, Reg32, 0 } },
+{"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm,      { RegXMM, LLongMem, 0 } },
+/* Intel mode string move.  */
+{"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
 {"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LongMem, 0 } },
 {"movupd",    2, 0x660f10,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1247,21 +1277,21 @@ static const template i386_optab[] = {
 {"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
 {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, Reg32, 0 } },
+{"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
 {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, FP|Modrm,      { RegXMM|WordMem, Reg32, 0 } },
-{"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
-{"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM, 0 } },
+{"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
+{"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,      { RegXMM|InvMem, RegXMM, 0 } },
 {"movdqa",    2, 0x660f6f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"movdqa",    2, 0x660f7f,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
 {"movdqu",    2, 0xf30f6f,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"movdqu",    2, 0xf30f7f,  X, CpuSSE2, FP|Modrm,      { RegXMM, RegXMM|LLongMem, 0 } },
-{"movq2q",    2, 0xf20fd6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
-{"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegMMX, 0 } },
+{"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, FP|Modrm,     { RegXMM|InvMem, RegMMX, 0 } },
+{"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, FP|Modrm,      { RegMMX|InvMem, RegXMM, 0 } },
 {"pmuludq",   2, 0x0ff4,    X, CpuSSE2, FP|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
 {"pmuludq",   2, 0x660ff4,  X, CpuSSE2, FP|Modrm,      { RegXMM|LongMem, RegXMM, 0 } },
 {"pshufd",    3, 0x660f70,  X, CpuSSE2, FP|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
@@ -1270,6 +1300,31 @@ static const template i386_optab[] = {
 {"pslldq",    2, 0x660f73,  7, CpuSSE2, FP|Modrm,      { Imm8, RegXMM, 0 } },
 {"psrldq",    2, 0x660f73,  3, CpuSSE2, FP|Modrm,      { Imm8, RegXMM, 0 } },
 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, FP|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
+
+/* Prescott New Instructions.  */
+
+{"addsubpd",  2, 0x660fd0,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+/* Intel Syntax */
+{"fisttpd",   1, 0xdd,      1, CpuPNI, FP|Modrm,       { LLongMem, 0, 0} },
+{"fisttpq",   1, 0xdd,      1, CpuPNI, FP|Modrm,       { LLongMem, 0, 0} },
+{"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,       { LLongMem, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuPNI, FP|Modrm,       { LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,      { 0, 0, 0} },
+/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
+{"monitor",   3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,      { Reg32, Reg32, Reg32} },
+{"movddup",   2, 0xf20f12,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuPNI, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,      { 0, 0, 0} },
+/* Need to ensure only "mwait %eax,%ecx" is accepted.  */
+{"mwait",     2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,      { Reg32, Reg32, 0} },
 
 /* AMD 3DNow! instructions.  */
 
@@ -1302,9 +1357,9 @@ static const template i386_optab[] = {
 {"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },
 
 /* AMD extensions. */
-{"syscall",    0,0x0f05, X, CpuK6,      NoSuf,                 { 0, 0, 0} },
-{"sysret",     0,0x0f07, X, CpuK6,      lq_Suf|DefaultSize,    { 0, 0, 0} },
-{"swapgs",     0,0x0f01, 7, Cpu64,      NoSuf,                 { 0, 0, 0} },
+{"syscall",  0, 0x0f05,    X, CpuK6,   NoSuf,                  { 0, 0, 0} },
+{"sysret",   0, 0x0f07,    X, CpuK6,   lq_Suf|DefaultSize,     { 0, 0, 0} },
+{"swapgs",   0, 0x0f01, 0xf8, Cpu64,   NoSuf|ImmExt,           { 0, 0, 0} },
 
 /* sentinel */
 {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
@@ -1337,6 +1392,7 @@ static const reg_entry i386_regtab[] = {
   /* make %st first as we test for it */
   {"st", FloatReg|FloatAcc, 0, 0},
   /* 8 bit regs */
+#define REGNAM_AL 1            /* Entry in i386_regtab.  */
   {"al", Reg8|Acc, 0, 0},
   {"cl", Reg8|ShiftCount, 0, 1},
   {"dl", Reg8, 0, 2},
@@ -1362,6 +1418,7 @@ static const reg_entry i386_regtab[] = {
   {"r14b", Reg8, RegRex64|RegRex, 6},
   {"r15b", Reg8, RegRex64|RegRex, 7},
   /* 16 bit regs */
+#define REGNAM_AX 25
   {"ax", Reg16|Acc, 0, 0},
   {"cx", Reg16, 0, 1},
   {"dx", Reg16|InOutPortReg, 0, 2},
@@ -1379,6 +1436,7 @@ static const reg_entry i386_regtab[] = {
   {"r14w", Reg16, RegRex, 6},
   {"r15w", Reg16, RegRex, 7},
   /* 32 bit regs */
+#define REGNAM_EAX 41
   {"eax", Reg32|BaseIndex|Acc, 0, 0},  /* Must be in ax + 16 slot */
   {"ecx", Reg32|BaseIndex, 0, 1},
   {"edx", Reg32|BaseIndex, 0, 2},