gas/

[deliverable/binutils-gdb.git] / include / opcode / ia64.h

diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index d4e6d108137fca3d8540f16ed687638139fe7cf3..280862dfbcc413d323eeb2d8db2d5b5994688050 100644 (file)
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -1,7 +1,7 @@
 /* ia64.h -- Header file for ia64 opcode table
-   Copyright (C) 1998, 1999, 2002 David Mosberger-Tang <davidm@hpl.hp.com>
-
-   See the file HP-COPYRIGHT for additional information.  */
+   Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
+   Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
 
 #ifndef opcode_ia64_h
 #define opcode_ia64_h
@@ -39,13 +39,14 @@ enum ia64_unit
   };
 
 /* Changes to this enumeration must be propagated to the operand table in
-   bfd/cpu-ia64-opc.c 
- */ 
+   bfd/cpu-ia64-opc.c
+ */
 enum ia64_opnd
   {
     IA64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 
     /* constants */
+    IA64_OPND_AR_CSD,  /* application register csd (ar.csd) */
     IA64_OPND_AR_CCV,  /* application register ccv (ar.ccv) */
     IA64_OPND_AR_PFS,  /* application register pfs (ar.pfs) */
     IA64_OPND_C1,      /* the constant 1 */
@@ -75,13 +76,15 @@ enum ia64_opnd
     IA64_OPND_R3,      /* third register # */
     IA64_OPND_R3_2,    /* third register # (limited to gr0-gr3) */
 
+    /* memory operands: */
+    IA64_OPND_MR3,     /* memory at addr of third register # */
+
     /* indirect operands: */
     IA64_OPND_CPUID_R3,        /* cpuid[reg] */
     IA64_OPND_DBR_R3,  /* dbr[reg] */
     IA64_OPND_DTR_R3,  /* dtr[reg] */
     IA64_OPND_ITR_R3,  /* itr[reg] */
     IA64_OPND_IBR_R3,  /* ibr[reg] */
-    IA64_OPND_MR3,     /* memory at addr of third register # */
     IA64_OPND_MSR_R3,  /* msr[reg] */
     IA64_OPND_PKR_R3,  /* pkr[reg] */
     IA64_OPND_PMC_R3,  /* pmc[reg] */
@@ -100,6 +103,7 @@ enum ia64_opnd
     IA64_OPND_CPOS6c,  /* 6-bit count (63 - bits 31-36) */
     IA64_OPND_IMM1,    /* signed 1-bit immediate (bit 36) */
     IA64_OPND_IMMU2,   /* unsigned 2-bit immediate (bits 13-14) */
+    IA64_OPND_IMMU5b,  /* unsigned 5-bit immediate (32 + bits 14-18) */
     IA64_OPND_IMMU7a,  /* unsigned 7-bit immediate (bits 13-19) */
     IA64_OPND_IMMU7b,  /* unsigned 7-bit immediate (bits 20-26) */
     IA64_OPND_SOF,     /* 8-bit stack frame size */
@@ -133,6 +137,7 @@ enum ia64_opnd
     IA64_OPND_TGT25b,  /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
     IA64_OPND_TGT25c,  /* signed 25-bit (ip + 16*bits 13-32, 36) */
     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+    IA64_OPND_LDXMOV,  /* any symbol, generates R_IA64_LDXMOV.  */
 
     IA64_OPND_COUNT    /* # of operand types (MUST BE LAST!) */
   };
@@ -166,9 +171,10 @@ enum ia64_resource_specifier
   IA64_RS_BR,
   IA64_RS_CFM,
   IA64_RS_CPUID,
+  IA64_RS_CR_IIB,
   IA64_RS_CR_IRR,
   IA64_RS_CR_LRR,
-  IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
+  IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
   IA64_RS_DBR,
   IA64_RS_FR,
   IA64_RS_FRb,
@@ -287,7 +293,7 @@ struct ia64_opcode
     /* Used by ia64_find_next_opcode (). */
     short ent_index;
 
-    /* Opcode dependencies. */ 
+    /* Opcode dependencies. */
     const struct ia64_opcode_dependency *dependencies;
   };