/* Opcode table header for m680[01234]0/m6888[12]/m68851.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
- 2003, 2004 Free Software Foundation, Inc.
+ 2003, 2004, 2006 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
/* These are used as bit flags for the arch field in the m68k_opcode
structure. */
#define _m68k_undef 0
#define m68000 0x001
-#define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
#define m68010 0x002
#define m68020 0x004
#define m68030 0x008
-#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
- gas will deal with the few differences. */
#define m68040 0x010
-/* There is no 68050. */
#define m68060 0x020
#define m68881 0x040
-#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
#define m68851 0x080
#define cpu32 0x100 /* e.g., 68332 */
-
-#define mcfmac 0x200 /* ColdFire MAC. */
-#define mcfemac 0x400 /* ColdFire EMAC. */
-#define cfloat 0x800 /* ColdFire FPU. */
-#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
-
-#define mcfisa_a 0x2000 /* ColdFire ISA_A. */
-#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
-#define mcfisa_b 0x8000 /* ColdFire ISA_B. */
-#define mcfusp 0x10000 /* ColdFire USP instructions. */
-
-#define mcf5200 0x20000
-#define mcf5206e 0x40000
-#define mcf521x 0x80000
-#define mcf5249 0x100000
-#define mcf528x 0x200000
-#define mcf5307 0x400000
-#define mcf5407 0x800000
-#define mcf5470 0x1000000
-#define mcf5480 0x2000000
-
- /* Handy aliases. */
+#define fido_a 0x200
+#define m68k_mask 0x3ff
+
+#define mcfmac 0x400 /* ColdFire MAC. */
+#define mcfemac 0x800 /* ColdFire EMAC. */
+#define cfloat 0x1000 /* ColdFire FPU. */
+#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */
+
+#define mcfisa_a 0x4000 /* ColdFire ISA_A. */
+#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */
+#define mcfisa_b 0x10000 /* ColdFire ISA_B. */
+#define mcfisa_c 0x20000 /* ColdFire ISA_C. */
+#define mcfusp 0x40000 /* ColdFire USP instructions. */
+#define mcf_mask 0x7e400
+
+/* Handy aliases. */
#define m68040up (m68040 | m68060)
#define m68030up (m68030 | m68040up)
#define m68020up (m68020 | m68030up)
-#define m68010up (m68010 | cpu32 | m68020up)
+#define m68010up (m68010 | cpu32 | fido_a | m68020up)
#define m68000up (m68000 | m68010up)
-#define mfloat (m68881 | m68882 | m68040 | m68060)
+#define mfloat (m68881 | m68040 | m68060)
#define mmmu (m68851 | m68030 | m68040 | m68060)
/* The structure used to hold information for an opcode. */
{
/* The opcode name. */
const char *name;
+ /* The pseudo-size of the instruction(in bytes). Used to determine
+ number of bytes necessary to disassemble the instruction. */
+ unsigned int size;
/* The opcode itself. */
unsigned long opcode;
/* The mask used by the disassembler. */
The args field is a string containing two characters for each
operand of the instruction. The first specifies the kind of
- operand; the second, the place it is stored. */
+ operand; the second, the place it is stored.
+
+ If the first char of args is '.', it indicates that the opcode is
+ two words. This is only necessary when the match field does not
+ have any bits set in the second opcode word. Such a '.' is skipped
+ for operand processing. */
/* Kinds of operands:
- Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
+ Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
! control (modes 2,5,6,7.0-3)
(not 0,1,3,4,7.4)
& alterable control (modes 2,5,6,7.0,7.1)
- (not 0,1,7.2-4)
+ (not 0,1,3,4,7.2-4)
$ alterable data (modes 0,2-6,7.0,7.1)
(not 1,7.2-4)
? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
y (modes 2,5)
z (modes 2,5,7.2)
x mov3q immediate operand.
+ j coprocessor ET operand.
+ K coprocessor command number.
4 (modes 2,3,4,5)
*/
7 second word, shifted 7
8 second word, shifted 10
9 second word, shifted 5
+ E second word, shifted 9
D store in both place 1 and place 3; for divul and divsl.
B first word, low byte, for branch displacements
W second word (entire), for branch displacements
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