gas/

[deliverable/binutils-gdb.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 5691ac535b28430643532ed238a2f2950c1173fc..0bb9c11870d704b4d4f6a83475e3c100e14f9ded 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1,6 +1,6 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2008, 2009, 2010
+   2003, 2004, 2005, 2008, 2009, 2010, 2013
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -212,6 +212,10 @@
 #define        OP_OP_SDC2              0x3e
 #define        OP_OP_SDC3              0x3f    /* a.k.a. sd */
 
+/* MIPS VIRT ASE */
+#define OP_MASK_CODE10         0x3ff
+#define OP_SH_CODE10           11
+
 /* Values in the 'VSEL' field.  */
 #define MDMX_FMTSEL_IMM_QH     0x1d
 #define MDMX_FMTSEL_IMM_OB     0x1e
@@ -255,8 +259,6 @@
    of the operand handling in GAS.  The fields below only exist
    in the microMIPS encoding, so define each one to have an empty
    range.  */
-#define OP_MASK_CODE10         0
-#define OP_SH_CODE10           0
 #define OP_MASK_TRAP           0
 #define OP_SH_TRAP             0
 #define OP_MASK_OFFSET10       0
@@ -355,6 +357,9 @@ struct mips_opcode
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is a member. */
   unsigned long membership;
+  /* A collection of bits describing the ASE of which this instruction
+     or macro is a member.  */
+  unsigned long ase;
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is not a member.  */
   unsigned long exclusions;
@@ -486,6 +491,9 @@ struct mips_opcode
    "~" 12 bit offset (OP_*_OFFSET12)
    "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 
+   VIRT ASE usage:
+   "+J" 10-bit hypcall code (OP_*CODE10)
+
    UDI immediates:
    "+1" UDI immediate bits 6-10
    "+2" UDI immediate bits 6-15
@@ -528,7 +536,7 @@ struct mips_opcode
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    "1234"
-   "ABCDEFGHIPQSTXZ"
+   "ABCDEFGHIJPQSTXZ"
    "abcpstxz"
 */
 
@@ -726,16 +734,10 @@ static const unsigned int mips_isa_table[] =
 #define INSN_OCTEON2             0x00000100
 
 /* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK            0x3c00f010
+#define INSN_ASE_MASK            0x3c00f0d0
 
-/* DSP ASE */ 
-#define INSN_DSP                  0x00001000
-#define INSN_DSP64                0x00002000
-
-/* 0x00004000 is unused.  */
-
-/* MIPS-3D ASE */
-#define INSN_MIPS3D               0x00008000
+/* MIPS R5900 instruction */
+#define INSN_5900                 0x00004000
 
 /* MIPS R4650 instruction.  */
 #define INSN_4650                 0x00010000
@@ -758,14 +760,6 @@ static const unsigned int mips_isa_table[] =
 /* NEC VR5500 instruction.  */
 #define INSN_5500                0x02000000
 
-/* MDMX ASE */ 
-#define INSN_MDMX                 0x04000000
-/* MT ASE */
-#define INSN_MT                   0x08000000
-/* SmartMIPS ASE  */
-#define INSN_SMARTMIPS            0x10000000
-/* DSP R2 ASE  */
-#define INSN_DSPR2                0x20000000
 /* ST Microelectronics Loongson 2E.  */
 #define INSN_LOONGSON_2E          0x40000000
 /* ST Microelectronics Loongson 2F.  */
@@ -773,10 +767,26 @@ static const unsigned int mips_isa_table[] =
 /* Loongson 3A.  */
 #define INSN_LOONGSON_3A          0x00000400
 /* RMI Xlr instruction */
-#define INSN_XLR                 0x00000020
+#define INSN_XLR                 0x00000020
 
+/* DSP ASE */
+#define ASE_DSP                        0x00000001
+#define ASE_DSP64              0x00000002
+/* DSP R2 ASE  */
+#define ASE_DSPR2              0x00000004
 /* MCU (MicroController) ASE */
-#define INSN_MCU                 0x00000010
+#define ASE_MCU                        0x00000010
+/* MDMX ASE */
+#define ASE_MDMX               0x00000020
+/* MIPS-3D ASE */
+#define ASE_MIPS3D             0x00000040
+/* MT ASE */
+#define ASE_MT                 0x00000080
+/* SmartMIPS ASE  */
+#define ASE_SMARTMIPS          0x00000100
+/* Virtualization ASE */
+#define ASE_VIRT               0x00000200
+#define ASE_VIRT64             0x00000400
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -811,6 +821,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_R5000      5000
 #define CPU_VR5400     5400
 #define CPU_VR5500     5500
+#define CPU_R5900      5900
 #define CPU_R6000      6000
 #define CPU_RM7000     7000
 #define CPU_R8000      8000
@@ -876,6 +887,9 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_VR5500:
       return (mask & INSN_5500) != 0;
 
+    case CPU_R5900:
+      return (mask & INSN_5900) != 0;
+
     case CPU_LOONGSON_2E:
       return (mask & INSN_LOONGSON_2E) != 0;
 
@@ -909,7 +923,7 @@ cpu_is_member (int cpu, unsigned int mask)
    if instruction INSN is available to the given ISA and CPU. */
 
 static inline bfd_boolean
-opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 {
   if (!cpu_is_member (cpu, insn->exclusions))
     {
@@ -921,7 +935,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
        return TRUE;
 
       /* Test for ASE compatibility.  */
-      if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+      if ((ase & insn->ase) != 0)
        return TRUE;
 
       /* Test for processor-specific extensions.  */
@@ -1056,6 +1070,7 @@ enum
   M_LDC1_AB,
   M_LDC2_AB,
   M_LDC2_OB,
+  M_LQC2_AB,
   M_LDC3_AB,
   M_LDL_AB,
   M_LDL_OB,
@@ -1078,6 +1093,7 @@ enum
   M_LL_OB,
   M_LLD_AB,
   M_LLD_OB,
+  M_LQ_AB,
   M_LS_A,
   M_LW_A,
   M_LW_AB,
@@ -1148,6 +1164,7 @@ enum
   M_SDC1_AB,
   M_SDC2_AB,
   M_SDC2_OB,
+  M_SQC2_AB,
   M_SDC3_AB,
   M_SDL_AB,
   M_SDL_OB,
@@ -1179,6 +1196,7 @@ enum
   M_SB_AB,
   M_SH_A,
   M_SH_AB,
+  M_SQ_AB,
   M_SW_A,
   M_SW_AB,
   M_SWC0_A,