/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993 Free Software Foundation, Inc.
+ Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _MIPS_H_
+#define _MIPS_H_
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
- only use ten bits).
+ only use ten bits). An optional two-operand form of break/sdbbp
+ allows the lower ten bits to be set too.
The syscall instruction uses SYSCALL.
#define OP_SH_OP 26
#define OP_MASK_RS 0x1f
#define OP_SH_RS 21
+#define OP_MASK_FR 0x1f
+#define OP_SH_FR 21
#define OP_MASK_FMT 0x1f
#define OP_SH_FMT 21
+#define OP_MASK_BCC 0x7
+#define OP_SH_BCC 18
#define OP_MASK_CODE 0x3ff
#define OP_SH_CODE 16
+#define OP_MASK_CODE2 0x3ff
+#define OP_SH_CODE2 6
#define OP_MASK_RT 0x1f
#define OP_SH_RT 16
#define OP_MASK_FT 0x1f
#define OP_SH_FT 16
+#define OP_MASK_CACHE 0x1f
+#define OP_SH_CACHE 16
#define OP_MASK_RD 0x1f
#define OP_SH_RD 11
#define OP_MASK_FS 0x1f
#define OP_SH_FS 11
+#define OP_MASK_PREFX 0x1f
+#define OP_SH_PREFX 11
+#define OP_MASK_CCC 0x7
+#define OP_SH_CCC 8
#define OP_MASK_SYSCALL 0xfffff
#define OP_SH_SYSCALL 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_FUNCT 0
#define OP_MASK_SPEC 0x3f
#define OP_SH_SPEC 0
+#define OP_SH_LOCC 8 /* FP condition code */
+#define OP_SH_HICC 18 /* FP condition code */
+#define OP_MASK_CC 0x7
+#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */
+#define OP_MASK_COP1NORM 0x1 /* a single bit */
+#define OP_SH_COP1SPEC 21 /* COP1 encodings */
+#define OP_MASK_COP1SPEC 0xf
+#define OP_MASK_COP1SCLR 0x4
+#define OP_MASK_COP1CMP 0x3
+#define OP_SH_COP1CMP 4
+#define OP_SH_FORMAT 21 /* FP short format field */
+#define OP_MASK_FORMAT 0x7
+#define OP_SH_TRUE 16
+#define OP_MASK_TRUE 0x1
+#define OP_SH_GE 17
+#define OP_MASK_GE 0x01
+#define OP_SH_UNSIGNED 16
+#define OP_MASK_UNSIGNED 0x1
+#define OP_SH_HINT 16
+#define OP_MASK_HINT 0x1f
+#define OP_SH_MMI 0 /* Multimedia (parallel) op */
+#define OP_MASK_MMI 0x3f
+#define OP_SH_MMISUB 6
+#define OP_MASK_MMISUB 0x1f
+#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
+#define OP_SH_PERFREG 1
/* This structure holds information for a particular instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
- that is used. */
+ that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
+ /* A collection of bits describing the instruction sets of which this
+ instruction or macro is a member. */
+ unsigned long membership;
};
/* These are the characters which may appears in the args field of an
Each of these characters corresponds to a mask field defined above.
"<" 5 bit shift amount (OP_*_SHAMT)
+ ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD)
+ "h" 5 bit prefx hint (OP_*_PREFX)
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
+ "k" 5 bit cache opcode in target register position (OP_*_CACHE)
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
+ "q" 10 bit extra breakpoint code (OP_*_CODE2)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
"t" 5 bit target register (OP_*_RT)
"w" 5 bit same register used as both target and destination (OP_*_RT)
"C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall function code (OP_*_SYSCALL)
+ "x" accept and ignore register name
+ "z" must be zero register
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
+ "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
+ "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
"S" 5 bit fs source 1 register (OP_*_FS)
"T" 5 bit ft source 2 register (OP_*_FT)
+ "R" 5 bit fr source 3 register (OP_*_FR)
"V" 5 bit same register used as floating source and destination (OP_*_FS)
"W" 5 bit same register used as floating target and destination (OP_*_FT)
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
+ "P" 5 bit performance-monitor register (OP_*_PERFREG)
Macro instructions:
+ "A" General 32 bit expression
"I" 32 bit immediate
- "F" 64 bit floating point constant
+ "F" 64 bit floating point constant in .rdata
+ "L" 64 bit floating point constant in .lit8
+ "f" 32 bit floating point constant
+ "l" 32 bit floating point constant in .lit4
+
+ Other:
+ "()" parens surrounding optional value
+ "," separates operands
+
+ Characters used so far, for quick reference when adding more:
+ "<>(),"
+ "ABCDEFGILMNSTRVW"
+ "abcdfhijklopqrstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
/* Modifies the general purpose register in OP_*_RD. */
#define INSN_WRITE_GPR_D 0x00000001
-/* Modifies the general purpose register in OP_*_RS. */
-#define INSN_WRITE_GPR_S 0x00000002
/* Modifies the general purpose register in OP_*_RT. */
-#define INSN_WRITE_GPR_T 0x00000004
+#define INSN_WRITE_GPR_T 0x00000002
/* Modifies general purpose register 31. */
-#define INSN_WRITE_GPR_31 0x00000008
-/* Modifies the floating point register in OP_*_RD. */
-#define INSN_WRITE_FPR_D 0x00000010
-/* Modifies the floating point register in OP_*_RS. */
-#define INSN_WRITE_FPR_S 0x00000020
-/* Modifies the floating point register in OP_*_RT. */
-#define INSN_WRITE_FPR_T 0x00000040
-/* Reads the general purpose register in OP_*_RD. */
-#define INSN_READ_GPR_D 0x00000080
+#define INSN_WRITE_GPR_31 0x00000004
+/* Modifies the floating point register in OP_*_FD. */
+#define INSN_WRITE_FPR_D 0x00000008
+/* Modifies the floating point register in OP_*_FS. */
+#define INSN_WRITE_FPR_S 0x00000010
+/* Modifies the floating point register in OP_*_FT. */
+#define INSN_WRITE_FPR_T 0x00000020
/* Reads the general purpose register in OP_*_RS. */
-#define INSN_READ_GPR_S 0x00000100
+#define INSN_READ_GPR_S 0x00000040
/* Reads the general purpose register in OP_*_RT. */
-#define INSN_READ_GPR_T 0x00000200
-/* Reads general purpose register 31 (FIXME: no instruction does this). */
-#define INSN_READ_GPR_31 0x00000400
-/* Reads the floating point register in OP_*_RD. */
-#define INSN_READ_FPR_D 0x00000800
-/* Reads the floating point register in OP_*_RS. */
-#define INSN_READ_FPR_S 0x00001000
-/* Reads the floating point register in OP_*_RT. */
-#define INSN_READ_FPR_T 0x00002000
-/* Takes a trap (FIXME: why is this interesting?). */
-#define INSN_TRAP 0x00004000
-/* Sets coprocessor condition code. */
-#define INSN_COND_CODE 0x00008000
+#define INSN_READ_GPR_T 0x00000080
+/* Reads the floating point register in OP_*_FS. */
+#define INSN_READ_FPR_S 0x00000100
+/* Reads the floating point register in OP_*_FT. */
+#define INSN_READ_FPR_T 0x00000200
+/* Reads the floating point register in OP_*_FR. */
+#define INSN_READ_FPR_R 0x00000400
+/* Modifies coprocessor condition code. */
+#define INSN_WRITE_COND_CODE 0x00000800
+/* Reads coprocessor condition code. */
+#define INSN_READ_COND_CODE 0x00001000
/* TLB operation. */
-#define INSN_TLB 0x00010000
-/* RFE (return from exception) instruction. */
-#define INSN_RFE 0x00020000
-/* Coprocessor instruction. */
-#define INSN_COP 0x00040000
-/* Instruction destination requires load delay. */
-#define INSN_LOAD_DELAY 0x00080000
+#define INSN_TLB 0x00002000
+/* Reads coprocessor register other than floating point register. */
+#define INSN_COP 0x00004000
+/* Instruction loads value from memory, requiring delay. */
+#define INSN_LOAD_MEMORY_DELAY 0x00008000
+/* Instruction loads value from coprocessor, requiring delay. */
+#define INSN_LOAD_COPROC_DELAY 0x00010000
/* Instruction has unconditional branch delay slot. */
-#define INSN_UNCOND_BRANCH_DELAY 0x00100000
+#define INSN_UNCOND_BRANCH_DELAY 0x00020000
/* Instruction has conditional branch delay slot. */
-#define INSN_COND_BRANCH_DELAY 0x00200000
-/* Instruction requires coprocessor delay. */
-#define INSN_COPROC_DELAY 0x00400000
+#define INSN_COND_BRANCH_DELAY 0x00040000
+/* Conditional branch likely: if branch not taken, insn nullified. */
+#define INSN_COND_BRANCH_LIKELY 0x00080000
+/* Moves to coprocessor register, requiring delay. */
+#define INSN_COPROC_MOVE_DELAY 0x00100000
+/* Loads coprocessor register from memory, requiring delay. */
+#define INSN_COPROC_MEMORY_DELAY 0x00200000
/* Reads the HI register. */
-#define INSN_READ_HI 0x00800000
+#define INSN_READ_HI 0x00400000
/* Reads the LO register. */
-#define INSN_READ_LO 0x01000000
+#define INSN_READ_LO 0x00800000
/* Modifies the HI register. */
-#define INSN_WRITE_HI 0x02000000
+#define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */
-#define INSN_WRITE_LO 0x04000000
-/* R4000 instruction. */
-#define INSN_R4000 0x80000000
+#define INSN_WRITE_LO 0x02000000
+/* Takes a trap (easier to keep out of delay slot). */
+#define INSN_TRAP 0x04000000
+/* Instruction stores value into memory. */
+#define INSN_STORE_MEMORY 0x08000000
+/* Instruction uses single precision floating point. */
+#define FP_S 0x10000000
+/* Instruction uses double precision floating point. */
+#define FP_D 0x20000000
+/* Instruction is part of the tx39's integer multiply family. */
+#define INSN_MULT 0x40000000
+/* Instruction synchronize shared memory. */
+#define INSN_SYNC 0x80000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
+
+
+
+
+/* MIPS ISA field--CPU level at which insn is supported. */
+#define INSN_ISA 0x0000000F
+/* An instruction which is not part of any basic MIPS ISA.
+ (ie it is a chip specific instruction) */
+#define INSN_NO_ISA 0x00000000
+/* MIPS ISA 1 instruction. */
+#define INSN_ISA1 0x00000001
+/* MIPS ISA 2 instruction (R6000 or R4000). */
+#define INSN_ISA2 0x00000002
+/* MIPS ISA 3 instruction (R4000). */
+#define INSN_ISA3 0x00000003
+/* MIPS ISA 4 instruction (R8000). */
+#define INSN_ISA4 0x00000004
+#define INSN_ISA5 0x00000005
+
+/* Chip specific instructions. These are bitmasks. */
+/* MIPS R4650 instruction. */
+#define INSN_4650 0x00000010
+/* LSI R4010 instruction. */
+#define INSN_4010 0x00000020
+/* NEC VR4100 instruction. */
+#define INSN_4100 0x00000040
+/* Toshiba R3900 instruction. */
+#define INSN_3900 0x00000080
+
+/* 32-bit code running on a ISA3+ CPU. */
+#define INSN_GP32 0x00001000
+
+/* Test for membership in an ISA including chip specific ISAs.
+ INSN is pointer to an element of the opcode table; ISA is the
+ specified ISA to test against; and CPU is the CPU specific ISA
+ to test, or zero if no CPU specific ISA test is desired.
+ The gp32 arg is set when you need to force 32-bit register usage on
+ a machine with 64-bit registers; see the documentation under -mgp32
+ in the MIPS gas docs. */
+
+#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \
+ ((((insn)->membership & INSN_ISA) != 0 \
+ && ((insn)->membership & INSN_ISA) <= isa \
+ && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
+ || (cpu == 4650 \
+ && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == 4010 \
+ && ((insn)->membership & INSN_4010) != 0) \
+ || ((cpu == 4100 \
+ || cpu == 4111 \
+ ) \
+ && ((insn)->membership & INSN_4100) != 0) \
+ || (cpu == 3900 \
+ && ((insn)->membership & INSN_3900) != 0))
+
/* This is a list of macro expanded instructions.
*
* _I appended means immediate
* _A appended means address
* _AB appended means address with base register
- * _D appended means floating point constant
+ * _D appended means 64 bit floating point constant
+ * _S appended means 32 bit floating point constant
*/
enum {
M_ABS,
- M_ABSU,
M_ADD_I,
M_ADDU_I,
M_AND_I,
+ M_BEQ,
M_BEQ_I,
+ M_BEQL_I,
M_BGE,
+ M_BGEL,
M_BGE_I,
+ M_BGEL_I,
M_BGEU,
+ M_BGEUL,
M_BGEU_I,
+ M_BGEUL_I,
M_BGT,
+ M_BGTL,
M_BGT_I,
+ M_BGTL_I,
M_BGTU,
+ M_BGTUL,
M_BGTU_I,
+ M_BGTUL_I,
M_BLE,
+ M_BLEL,
M_BLE_I,
+ M_BLEL_I,
M_BLEU,
+ M_BLEUL,
M_BLEU_I,
+ M_BLEUL_I,
M_BLT,
+ M_BLTL,
M_BLT_I,
+ M_BLTL_I,
M_BLTU,
+ M_BLTUL,
M_BLTU_I,
+ M_BLTUL_I,
+ M_BNE,
M_BNE_I,
+ M_BNEL_I,
+ M_DABS,
+ M_DADD_I,
+ M_DADDU_I,
+ M_DDIV_3,
+ M_DDIV_3I,
+ M_DDIVU_3,
+ M_DDIVU_3I,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
M_DIVU_3I,
+ M_DLA_AB,
+ M_DLI,
+ M_DMUL,
+ M_DMUL_I,
+ M_DMULO,
+ M_DMULO_I,
+ M_DMULOU,
+ M_DMULOU_I,
+ M_DREM_3,
+ M_DREM_3I,
+ M_DREMU_3,
+ M_DREMU_3I,
+ M_DSUB_I,
+ M_DSUBU_I,
+ M_DSUBU_I_2,
+ M_J_A,
+ M_JAL_1,
+ M_JAL_2,
+ M_JAL_A,
M_L_DOB,
M_L_DAB,
- M_LA,
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
+ M_LDC1_AB,
+ M_LDC2_AB,
+ M_LDC3_AB,
+ M_LDL_AB,
+ M_LDR_AB,
M_LH_A,
M_LH_AB,
M_LHU_A,
M_LI,
M_LI_D,
M_LI_DD,
+ M_LI_S,
+ M_LI_SS,
+ M_LL_AB,
+ M_LLD_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWL_AB,
M_LWR_A,
M_LWR_AB,
+ M_LWU_AB,
M_MUL,
M_MUL_I,
M_MULO,
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SC_AB,
+ M_SCD_AB,
M_SD_A,
M_SD_OB,
M_SD_AB,
+ M_SDC1_AB,
+ M_SDC2_AB,
+ M_SDC3_AB,
+ M_SDL_AB,
+ M_SDR_AB,
M_SEQ,
M_SEQ_I,
M_SGE,
M_SWR_AB,
M_SUB_I,
M_SUBU_I,
+ M_SUBU_I_2,
+ M_TEQ_I,
+ M_TGE_I,
+ M_TGEU_I,
+ M_TLT_I,
+ M_TLTU_I,
+ M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
+ M_ULD,
+ M_ULD_A,
M_ULH,
M_ULH_A,
M_ULHU,
M_USH_A,
M_USW,
M_USW_A,
- M_XOR_I
+ M_USD,
+ M_USD_A,
+ M_XOR_I,
+ M_COP0,
+ M_COP1,
+ M_COP2,
+ M_COP3,
+ M_NUM_MACROS
};
-/* Short hand so the lines aren't too long. */
-
-#define LDD INSN_LOAD_DELAY
-#define UBD INSN_UNCOND_BRANCH_DELAY
-#define CBD INSN_COND_BRANCH_DELAY
-#define COD INSN_COPROC_DELAY
-#define EXD (INSN_READ_HI|INSN_READ_LO)
-
-/* True if this instruction may require a delay slot. */
-#define ANY_DELAY (LDD|UBD|CBD|COD|EXD)
-
-#define WR_d INSN_WRITE_GPR_D
-#define WR_s INSN_WRITE_GPR_S
-#define WR_t INSN_WRITE_GPR_T
-#define WR_31 INSN_WRITE_GPR_31
-#define WR_D INSN_WRITE_FPR_D
-#define WR_S INSN_WRITE_FPR_S
-#define WR_T INSN_WRITE_FPR_T
-#define RD_d INSN_READ_GPR_D
-#define RD_s INSN_READ_GPR_S
-#define RD_b INSN_READ_GPR_S
-#define RD_t INSN_READ_GPR_T
-#define ST_t INSN_READ_GPR_T
-#define RD_31 INSN_READ_GPR_31
-#define RD_D INSN_READ_FPR_D
-#define RD_S INSN_READ_FPR_S
-#define RD_T INSN_READ_FPR_T
-#define CC (INSN_COND_CODE|INSN_COPROC_DELAY)
-#define ST_T INSN_READ_FPR_T
-#define ST_C0 INSN_COP
-#define ST_C1 INSN_READ_FPR_T
-#define ST_C2 INSN_COP
-#define ST_C3 INSN_COP
-#define RD_C0 INSN_COP
-#define RD_C1 INSN_READ_FPR_T
-#define RD_C2 INSN_COP
-#define RD_C3 INSN_COP
-#define WR_C0 INSN_COP
-#define WR_C1 INSN_READ_FPR_T
-#define WR_C2 INSN_COP
-#define WR_C3 INSN_COP
-#define WR_HI INSN_WRITE_HI
-#define WR_LO INSN_WRITE_LO
-#define RD_HI INSN_READ_HI
-#define RD_LO INSN_READ_LO
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
-static const struct mips_opcode mips_opcodes[] = {
-/* These instructions appear first so that the disassembler will find
- them first. The assemblers uses a hash table based on the
- instruction name anyhow. */
-{"nop", "", 0x00000000, 0xffffffff, 0 },
-{"li", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
-{"li", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
-{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
-{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s }, /* addu */
-{"b", "p", 0x10000000, 0xffff0000, UBD }, /* beq 0,0 */
-{"b", "p", 0x40100000, 0xffff0000, UBD }, /* bgez 0 */
-{"bal", "p", 0x04110000, 0xffff0000, UBD }, /* bgezal 0 */
-
-{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
-{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
-{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S },
-{"absu", "d,s", 0, (int) M_ABSU, INSN_MACRO },
-{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
-{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T },
-{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T },
-{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s },
-{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s },
-{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
-{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
-{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s },
-/* b is at the top of the table. */
-/* bal is at the top of the table. */
-{"bc0f", "p", 0x41000000, 0xffff0000, CBD },
-{"bc1f", "p", 0x45000000, 0xffff0000, CBD },
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD },
-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD },
-{"bc0t", "p", 0x41010000, 0xffff0000, CBD },
-{"bc1t", "p", 0x45010000, 0xffff0000, CBD },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD },
-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD },
-{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
-{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
-{"beqz", "s,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
-{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
-{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
-{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
-{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
-{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s },
-{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s },
-{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
-{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
-{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
-{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
-{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s },
-{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
-{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
-{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
-{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
-{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s },
-{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
-{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
-{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
-{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
-{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s },
-{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s },
-{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
-{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
-{"bnez", "s,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
-{"break", "", 0x0000000d, 0xffffffff, INSN_TRAP },
-{"break", "c", 0x0000000d, 0xfc00003f, INSN_TRAP },
-{"c.f.d", "S,T", 0x46200030, 0xffe003ff, RD_S|RD_T|CC },
-{"c.f.s", "S,T", 0x46000030, 0xffe003ff, RD_S|RD_T|CC },
-{"c.un.d", "S,T", 0x46200031, 0xffe003ff, RD_S|RD_T|CC },
-{"c.un.s", "S,T", 0x46000031, 0xffe003ff, RD_S|RD_T|CC },
-{"c.eq.d", "S,T", 0x46200032, 0xffe003ff, RD_S|RD_T|CC },
-{"c.eq.s", "S,T", 0x46000032, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ueq.d", "S,T", 0x46200033, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ueq.s", "S,T", 0x46000033, 0xffe003ff, RD_S|RD_T|CC },
-{"c.olt.d", "S,T", 0x46200034, 0xffe003ff, RD_S|RD_T|CC },
-{"c.olt.s", "S,T", 0x46000034, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ult.d", "S,T", 0x46200035, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ult.s", "S,T", 0x46000035, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ole.d", "S,T", 0x46200036, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ole.s", "S,T", 0x46000036, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ule.d", "S,T", 0x46200037, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ule.s", "S,T", 0x46000037, 0xffe003ff, RD_S|RD_T|CC },
-{"c.sf.d", "S,T", 0x46200038, 0xffe003ff, RD_S|RD_T|CC },
-{"c.sf.s", "S,T", 0x46000038, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngle.d","S,T", 0x46200039, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngle.s","S,T", 0x46000039, 0xffe003ff, RD_S|RD_T|CC },
-{"c.seq.d", "S,T", 0x4620003a, 0xffe003ff, RD_S|RD_T|CC },
-{"c.seq.s", "S,T", 0x4600003a, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngl.d", "S,T", 0x4620003b, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngl.s", "S,T", 0x4600003b, 0xffe003ff, RD_S|RD_T|CC },
-{"c.lt.d", "S,T", 0x4620003c, 0xffe003ff, RD_S|RD_T|CC },
-{"c.lt.s", "S,T", 0x4600003c, 0xffe003ff, RD_S|RD_T|CC },
-{"c.nge.d", "S,T", 0x4620003d, 0xffe003ff, RD_S|RD_T|CC },
-{"c.nge.s", "S,T", 0x4600003d, 0xffe003ff, RD_S|RD_T|CC },
-{"c.le.d", "S,T", 0x4620003e, 0xffe003ff, RD_S|RD_T|CC },
-{"c.le.s", "S,T", 0x4600003e, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngt.d", "S,T", 0x4620003f, 0xffe003ff, RD_S|RD_T|CC },
-{"c.ngt.s", "S,T", 0x4600003f, 0xffe003ff, RD_S|RD_T|CC },
-#if 0
-/* these are not very safe to use, no bounds checking. */
-{"c0", "I", 0x42000000, 0xfe000000, 0 },
-{"c1", "I", 0x46000000, 0xfe000000, 0 },
-{"c2", "I", 0x4a000000, 0xfe000000, 0 },
-{"c3", "I", 0x4e000000, 0xfe000000, 0 },
-#endif
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, COD|RD_d },
-{"cfc1", "t,S", 0x44400000, 0xffe007ff, COD|RD_S },
-{"cfc1", "t,G", 0x44400000, 0xffe007ff, COD|RD_S },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, COD|RD_d },
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, COD|RD_d },
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|RD_d },
-{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t },
-{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|RD_d },
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|RD_d },
-{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S },
-{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S },
-{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S },
-{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S },
-{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S },
-{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S },
-{"div", "s,t", 0x0000001a, 0xfc00003f, RD_s|RD_t|WR_HI|WR_LO },
-{"div", "d,s,t", 0, (int) M_DIV_3, INSN_MACRO },
-{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
-{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T },
-{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T },
-{"divu", "s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
-{"divu", "d,s,t", 0, (int) M_DIVU_3, INSN_MACRO },
-{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
-{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
-{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
-{"j", "a", 0x08000000, 0xfc000000, UBD },
-{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_31 },
-{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },
-{"jal", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },/* jalr */
-{"jal", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },/* jalr $ra */
-{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31 },
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
-{"la", "t,A", 0, (int) M_LA, INSN_MACRO },
-{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
-{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b },
-{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
-{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b },
-{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
-{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
-{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
-{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b },
-{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
-{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b },
-{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
-/* li is at the start of the table. */
-{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
-{"li.d", "S,F", 0, (int) M_LI_DD, INSN_MACRO },
-{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t },
-{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b },
-{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, COD|RD_b },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
-{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, COD|RD_b },
-{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, COD|RD_b },
-{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
-{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, COD|RD_b }, /* lwc1 */
-{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, COD|RD_b },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, COD|RD_b },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
-{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b },
-{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
-{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b },
-{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, COD|WR_t|RD_C0 },
-{"mfc1", "t,S", 0x44000000, 0xffe007ff, COD|RD_S },
-{"mfc1", "t,G", 0x44000000, 0xffe007ff, COD|RD_C1 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, COD|WR_t|RD_C2 },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, COD|WR_t|RD_C3 },
-{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI },
-{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO },
-{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_t|RD_S },
-{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_t|RD_S },
-/* move is at the top of the table. */
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0 },
-{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t },
-{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_C1 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2 },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3 },
-{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI },
-{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO },
-{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T },
-{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T },
-{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
-{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
-{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
-{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
-{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
-{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
-{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
-{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
-{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t }, /* sub 0 */
-{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t }, /* subu 0 */
-{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S },
-{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S },
-/* nop is at the start of the table. */
-{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"nor", "d,v,I", 0, (int) M_NOR_I, INSN_MACRO },
-{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t }, /* nor d,s,zero */
-{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
-{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
-{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
-{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
-{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
-{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
-{"rfe", "", 0x42000010, 0xffffffff, INSN_RFE },
-{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
-{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
-{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
-{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
-{"sb", "t,o(b)", 0xa0000000, 0xfc000000, ST_t|RD_b },
-{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
-{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
-{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
-{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
-{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
-{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
-{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
-{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
-{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
-{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
-{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
-{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
-{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
-{"sh", "t,o(b)", 0xa4000000, 0xfc000000, ST_t|RD_b },
-{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
-{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
-{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
-{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
-{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
-{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s },
-{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s }, /* sllv */
-{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t },
-{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
-{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s },
-{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s },
-{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
-{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
-{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
-{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
-{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
-{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_t|RD_d },
-{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s },
-{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srlv */
-{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t },
-{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
-{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T },
-{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T },
-{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
-{"sw", "t,o(b)", 0xac000000, 0xfc000000, ST_t|RD_b },
-{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, ST_C0|RD_b },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
-{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, ST_T|RD_b },
-{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, ST_C1|RD_b },
-{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
-{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, ST_T|RD_b }, /* swc1 */
-{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, ST_C2|RD_b },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, ST_C3|RD_b },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
-{"swl", "t,o(b)", 0xa8000000, 0xfc000000, ST_t|RD_b },
-{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
-{"swr", "t,o(b)", 0xb8000000, 0xfc000000, ST_t|RD_b },
-{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
-{"syscall", "", 0x0000000c, 0xffffffff, INSN_TRAP },
-{"syscall", "B", 0x0000000c, 0xfc00003f, INSN_TRAP },
-{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
-{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
-{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
-{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
-{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
-{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
-{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
-{"ulh", "t,A", 0, (int) M_ULH_A, INSN_MACRO },
-{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
-{"ulhu", "t,A", 0, (int) M_ULHU_A, INSN_MACRO },
-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
-{"ulw", "t,A", 0, (int) M_ULW_A, INSN_MACRO },
-{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
-{"ush", "t,A", 0, (int) M_USH_A, INSN_MACRO },
-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
-{"usw", "t,A", 0, (int) M_USW_A, INSN_MACRO },
-{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t },
-{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
-{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s },
-};
+extern const struct mips_opcode mips_builtin_opcodes[];
+extern const int bfd_mips_num_builtin_opcodes;
+extern struct mips_opcode *mips_opcodes;
+extern int bfd_mips_num_opcodes;
+#define NUMOPCODES bfd_mips_num_opcodes
+
+\f
+/* The rest of this file adds definitions for the mips16 TinyRISC
+ processor. */
+
+/* These are the bitmasks and shift counts used for the different
+ fields in the instruction formats. Other than OP, no masks are
+ provided for the fixed portions of an instruction, since they are
+ not needed.
+
+ The I format uses IMM11.
+
+ The RI format uses RX and IMM8.
+
+ The RR format uses RX, and RY.
+
+ The RRI format uses RX, RY, and IMM5.
+
+ The RRR format uses RX, RY, and RZ.
+
+ The RRI_A format uses RX, RY, and IMM4.
+
+ The SHIFT format uses RX, RY, and SHAMT.
+
+ The I8 format uses IMM8.
+
+ The I8_MOVR32 format uses RY and REGR32.
+
+ The IR_MOV32R format uses REG32R and MOV32Z.
+
+ The I64 format uses IMM8.
+
+ The RI64 format uses RY and IMM5.
+ */
+
+#define MIPS16OP_MASK_OP 0x1f
+#define MIPS16OP_SH_OP 11
+#define MIPS16OP_MASK_IMM11 0x7ff
+#define MIPS16OP_SH_IMM11 0
+#define MIPS16OP_MASK_RX 0x7
+#define MIPS16OP_SH_RX 8
+#define MIPS16OP_MASK_IMM8 0xff
+#define MIPS16OP_SH_IMM8 0
+#define MIPS16OP_MASK_RY 0x7
+#define MIPS16OP_SH_RY 5
+#define MIPS16OP_MASK_IMM5 0x1f
+#define MIPS16OP_SH_IMM5 0
+#define MIPS16OP_MASK_RZ 0x7
+#define MIPS16OP_SH_RZ 2
+#define MIPS16OP_MASK_IMM4 0xf
+#define MIPS16OP_SH_IMM4 0
+#define MIPS16OP_MASK_REGR32 0x1f
+#define MIPS16OP_SH_REGR32 0
+#define MIPS16OP_MASK_REG32R 0x1f
+#define MIPS16OP_SH_REG32R 3
+#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
+#define MIPS16OP_MASK_MOVE32Z 0x7
+#define MIPS16OP_SH_MOVE32Z 0
+#define MIPS16OP_MASK_IMM6 0x3f
+#define MIPS16OP_SH_IMM6 5
+
+/* These are the characters which may appears in the args field of an
+ instruction. They appear in the order in which the fields appear
+ when the instruction is used. Commas and parentheses in the args
+ string are ignored when assembling, and written into the output
+ when disassembling.
-#define NUMOPCODES (sizeof(mips_opcodes)/sizeof(*mips_opcodes))
+ "y" 3 bit register (MIPS16OP_*_RY)
+ "x" 3 bit register (MIPS16OP_*_RX)
+ "z" 3 bit register (MIPS16OP_*_RZ)
+ "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
+ "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
+ "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
+ "0" zero register ($0)
+ "S" stack pointer ($sp or $29)
+ "P" program counter
+ "R" return address register ($ra or $31)
+ "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
+ "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+ "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
+ "a" 26 bit jump address
+ "e" 11 bit extension value
+ "l" register list for entry instruction
+ "L" register list for exit instruction
+
+ The remaining codes may be extended. Except as otherwise noted,
+ the full extended operand is a 16 bit signed value.
+ "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
+ ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
+ "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
+ "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
+ "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
+ "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
+ "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
+ "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
+ "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
+ "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
+ "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
+ "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
+ "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
+ "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
+ "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
+ "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
+ "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
+ "q" 11 bit branch address (MIPS16OP_*_IMM11)
+ "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
+ "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
+ "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
+ */
+
+/* For the mips16, we use the same opcode table format and a few of
+ the same flags. However, most of the flags are different. */
+
+/* Modifies the register in MIPS16OP_*_RX. */
+#define MIPS16_INSN_WRITE_X 0x00000001
+/* Modifies the register in MIPS16OP_*_RY. */
+#define MIPS16_INSN_WRITE_Y 0x00000002
+/* Modifies the register in MIPS16OP_*_RZ. */
+#define MIPS16_INSN_WRITE_Z 0x00000004
+/* Modifies the T ($24) register. */
+#define MIPS16_INSN_WRITE_T 0x00000008
+/* Modifies the SP ($29) register. */
+#define MIPS16_INSN_WRITE_SP 0x00000010
+/* Modifies the RA ($31) register. */
+#define MIPS16_INSN_WRITE_31 0x00000020
+/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
+#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
+/* Reads the register in MIPS16OP_*_RX. */
+#define MIPS16_INSN_READ_X 0x00000080
+/* Reads the register in MIPS16OP_*_RY. */
+#define MIPS16_INSN_READ_Y 0x00000100
+/* Reads the register in MIPS16OP_*_MOVE32Z. */
+#define MIPS16_INSN_READ_Z 0x00000200
+/* Reads the T ($24) register. */
+#define MIPS16_INSN_READ_T 0x00000400
+/* Reads the SP ($29) register. */
+#define MIPS16_INSN_READ_SP 0x00000800
+/* Reads the RA ($31) register. */
+#define MIPS16_INSN_READ_31 0x00001000
+/* Reads the program counter. */
+#define MIPS16_INSN_READ_PC 0x00002000
+/* Reads the general purpose register in MIPS16OP_*_REGR32. */
+#define MIPS16_INSN_READ_GPR_X 0x00004000
+/* Is a branch insn. */
+#define MIPS16_INSN_BRANCH 0x00010000
+
+/* The following flags have the same value for the mips16 opcode
+ table:
+ INSN_UNCOND_BRANCH_DELAY
+ INSN_COND_BRANCH_DELAY
+ INSN_COND_BRANCH_LIKELY (never used)
+ INSN_READ_HI
+ INSN_READ_LO
+ INSN_WRITE_HI
+ INSN_WRITE_LO
+ INSN_TRAP
+ INSN_ISA3
+ */
+
+extern const struct mips_opcode mips16_opcodes[];
+extern const int bfd_mips16_num_opcodes;
+
+#endif /* _MIPS_H_ */
projects / deliverable / binutils-gdb.git / blobdiff