A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
- only use ten bits).
+ only use ten bits). An optional two-operand form of break/sdbbp
+ allows the lower ten bits to be set too.
The syscall instruction uses SYSCALL.
#define OP_SH_BCC 18
#define OP_MASK_CODE 0x3ff
#define OP_SH_CODE 16
+#define OP_MASK_CODE2 0x3ff
+#define OP_SH_CODE2 6
#define OP_MASK_RT 0x1f
#define OP_SH_RT 16
#define OP_MASK_FT 0x1f
#define OP_MASK_MMI 0x3f
#define OP_SH_MMISUB 6
#define OP_MASK_MMISUB 0x1f
-/* start-sanitize-vr5400 */
#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
#define OP_SH_PERFREG 1
-#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
- but 0x8-0xf don't select bytes. */
-#define OP_SH_VECBYTE 22
-#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
-#define OP_SH_VECALIGN 21
-/* end-sanitize-vr5400 */
/* This structure holds information for a particular instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
- that is used. If pinfo is INSN_MACRO, then this is instead the
- ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
- etc.). */
+ that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
information. */
unsigned long pinfo;
/* A collection of bits describing the instruction sets of which this
- instruction is a member. */
+ instruction or macro is a member. */
unsigned long membership;
};
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
-start-sanitize-vr5400
- also vr5400 vector ops immediate operand
-end-sanitize-vr5400
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
+ "q" 10 bit extra breakpoint code (OP_*_CODE2)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
"t" 5 bit target register (OP_*_RT)
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
-start-sanitize-vr5400
"P" 5 bit performance-monitor register (OP_*_PERFREG)
- "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
- "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
- see also "k" above
-end-sanitize-vr5400
Macro instructions:
"A" General 32 bit expression
Other:
"()" parens surrounding optional value
"," separates operands
-start-sanitize-vr5400
- "[]" brackets around index for vector-op scalar operand specifier (vr5400)
-end-sanitize-vr5400
Characters used so far, for quick reference when adding more:
-start-sanitize-vr5400
- "Pe%[]" plus...
-end-sanitize-vr5400
"<>(),"
"ABCDEFGILMNSTRVW"
- "abcdfhijkloprstuvwxz"
+ "abcdfhijklopqrstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
#define FP_S 0x10000000
/* Instruction uses double precision floating point. */
#define FP_D 0x20000000
-
-/* As yet unused bits: 0x40000000 */
+/* Instruction is part of the tx39's integer multiply family. */
+#define INSN_MULT 0x40000000
+/* Instruction synchronize shared memory. */
+#define INSN_SYNC 0x80000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_ISA3 0x00000003
/* MIPS ISA 4 instruction (R8000). */
#define INSN_ISA4 0x00000004
+#define INSN_ISA5 0x00000005
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
#define INSN_4100 0x00000040
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00000080
-/* start-sanitize-vr5400 */
-/* NEC VR5400 instruction. */
-#define INSN_5400 0x00001000
-/* end-sanitize-vr5400 */
-/* start-sanitize-r5900 */
-/* Toshiba R5900 instruction */
-#define INSN_5900 0x00000100
-/* end-sanitize-r5900 */
-/* start-sanitize-tx49 */
-#define INSN_4900 0x00000200
-/* end-sanitize-tx49 */
+/* 32-bit code running on a ISA3+ CPU. */
+#define INSN_GP32 0x00001000
+
+/* Test for membership in an ISA including chip specific ISAs.
+ INSN is pointer to an element of the opcode table; ISA is the
+ specified ISA to test against; and CPU is the CPU specific ISA
+ to test, or zero if no CPU specific ISA test is desired.
+ The gp32 arg is set when you need to force 32-bit register usage on
+ a machine with 64-bit registers; see the documentation under -mgp32
+ in the MIPS gas docs. */
+
+#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \
+ ((((insn)->membership & INSN_ISA) != 0 \
+ && ((insn)->membership & INSN_ISA) <= isa \
+ && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
+ || (cpu == 4650 \
+ && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == 4010 \
+ && ((insn)->membership & INSN_4010) != 0) \
+ || ((cpu == 4100 \
+ || cpu == 4111 \
+ ) \
+ && ((insn)->membership & INSN_4100) != 0) \
+ || (cpu == 3900 \
+ && ((insn)->membership & INSN_3900) != 0))
/* This is a list of macro expanded instructions.
*
#define MIPS16_INSN_READ_PC 0x00002000
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
#define MIPS16_INSN_READ_GPR_X 0x00004000
+/* Is a branch insn. */
+#define MIPS16_INSN_BRANCH 0x00010000
/* The following flags have the same value for the mips16 opcode
table:
projects / deliverable / binutils-gdb.git / blobdiff