/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009, 2010
+ 2003, 2004, 2005, 2008, 2009, 2010, 2013
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
#ifndef _MIPS_H_
#define _MIPS_H_
+#include "bfd.h"
+
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
#define OP_SH_MTACC_D 13
#define OP_MASK_MTACC_D 0x3
+/* MIPS MCU ASE */
+#define OP_MASK_3BITPOS 0x7
+#define OP_SH_3BITPOS 12
+#define OP_MASK_OFFSET12 0xfff
+#define OP_SH_OFFSET12 0
+
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
#define OP_OP_SDC2 0x3e
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
+/* MIPS VIRT ASE */
+#define OP_MASK_CODE10 0x3ff
+#define OP_SH_CODE10 11
+
/* Values in the 'VSEL' field. */
#define MDMX_FMTSEL_IMM_QH 0x1d
#define MDMX_FMTSEL_IMM_OB 0x1e
of the operand handling in GAS. The fields below only exist
in the microMIPS encoding, so define each one to have an empty
range. */
-#define OP_MASK_CODE10 0
-#define OP_SH_CODE10 0
#define OP_MASK_TRAP 0
#define OP_SH_TRAP 0
-#define OP_MASK_OFFSET12 0
-#define OP_SH_OFFSET12 0
#define OP_MASK_OFFSET10 0
#define OP_SH_OFFSET10 0
#define OP_MASK_RS3 0
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
+/* Enhanced VA Scheme */
+#define OP_SH_EVAOFFSET 7
+#define OP_MASK_EVAOFFSET 0x1ff
+
/* This structure holds information for a particular instruction. */
struct mips_opcode
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
+ /* A collection of bits describing the ASE of which this instruction
+ or macro is a member. */
+ unsigned long ase;
+ /* A collection of bits describing the instruction sets of which this
+ instruction or macro is not a member. */
+ unsigned long exclusions;
};
/* These are the characters which may appear in the args field of an
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+ MCU ASE usage:
+ "~" 12 bit offset (OP_*_OFFSET12)
+ "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
+
+ VIRT ASE usage:
+ "+J" 10-bit hypcall code (OP_*CODE10)
+
UDI immediates:
"+1" UDI immediate bits 6-10
"+2" UDI immediate bits 6-15
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
+ Enhanced VA Scheme:
+ "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+
Other:
"()" parens surrounding optional value
"," separates operands
Characters used so far, for quick reference when adding more:
"1234567890"
- "%[]<>(),+:'@!$*&"
+ "%[]<>(),+:'@!$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234"
- "ABCDEFGHIPQSTXZ"
- "abcpstxz"
+ "ABCDEFGHIJPQSTXZ"
+ "abcjpstxz"
*/
/* These are the bits which may be set in the pinfo field of an
#define FP_D 0x20000000
/* Instruction is part of the tx39's integer multiply family. */
#define INSN_MULT 0x40000000
+/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
+#define INSN_WRITE_GPR_S 0x80000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
#define INSN2_BRANCH_DELAY_16BIT 0x00000400
/* Instruction has a branch delay slot that requires a 32-bit instruction. */
#define INSN2_BRANCH_DELAY_32BIT 0x00000800
-/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
-#define INSN2_WRITE_GPR_S 0x00001000
/* Reads the floating point register in MICROMIPSOP_*_FD. */
-#define INSN2_READ_FPR_D 0x00002000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MB. */
-#define INSN2_MOD_GPR_MB 0x00004000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MC. */
-#define INSN2_MOD_GPR_MC 0x00008000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MD. */
-#define INSN2_MOD_GPR_MD 0x00010000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_ME. */
-#define INSN2_MOD_GPR_ME 0x00020000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MF. */
-#define INSN2_MOD_GPR_MF 0x00040000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MG. */
-#define INSN2_MOD_GPR_MG 0x00080000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MJ. */
-#define INSN2_MOD_GPR_MJ 0x00100000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MP. */
-#define INSN2_MOD_GPR_MP 0x00200000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MQ. */
-#define INSN2_MOD_GPR_MQ 0x00400000
+#define INSN2_READ_FPR_D 0x00001000
+/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
+#define INSN2_WRITE_GPR_MB 0x00002000
+/* Reads the general purpose register in MICROMIPSOP_*_MC. */
+#define INSN2_READ_GPR_MC 0x00004000
+/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
+#define INSN2_MOD_GPR_MD 0x00008000
+/* Reads the general purpose register in MICROMIPSOP_*_ME. */
+#define INSN2_READ_GPR_ME 0x00010000
+/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
+#define INSN2_MOD_GPR_MF 0x00020000
+/* Reads the general purpose register in MICROMIPSOP_*_MG. */
+#define INSN2_READ_GPR_MG 0x00040000
+/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
+#define INSN2_READ_GPR_MJ 0x00080000
+/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
+#define INSN2_WRITE_GPR_MJ 0x00100000
+/* Reads the general purpose register in MICROMIPSOP_*_MP. */
+#define INSN2_READ_GPR_MP 0x00200000
+/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
+#define INSN2_WRITE_GPR_MP 0x00400000
+/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
+#define INSN2_READ_GPR_MQ 0x00800000
/* Reads/Writes the stack pointer ($29). */
-#define INSN2_MOD_SP 0x00800000
+#define INSN2_MOD_SP 0x01000000
/* Reads the RA ($31) register. */
-#define INSN2_READ_GPR_31 0x01000000
+#define INSN2_READ_GPR_31 0x02000000
/* Reads the global pointer ($28). */
-#define INSN2_READ_GP 0x02000000
+#define INSN2_READ_GP 0x04000000
/* Reads the program counter ($pc). */
-#define INSN2_READ_PC 0x04000000
+#define INSN2_READ_PC 0x08000000
/* Is an unconditional branch insn. */
-#define INSN2_UNCOND_BRANCH 0x08000000
+#define INSN2_UNCOND_BRANCH 0x10000000
/* Is a conditional branch insn. */
-#define INSN2_COND_BRANCH 0x10000000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MH/I. */
-#define INSN2_MOD_GPR_MHI 0x20000000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MM. */
-#define INSN2_MOD_GPR_MM 0x40000000
-/* Reads/Writes the general purpose registers in MICROMIPSOP_*_MN. */
-#define INSN2_MOD_GPR_MN 0x80000000
+#define INSN2_COND_BRANCH 0x20000000
+/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
+#define INSN2_WRITE_GPR_MHI 0x40000000
+/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
+#define INSN2_READ_GPR_MMN 0x80000000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0c20
+#define INSN_CHIP_MASK 0xc3ff0f20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
+#define INSN_OCTEONP 0x00000200
+#define INSN_OCTEON2 0x00000100
-/* Masks used for MIPS-defined ASEs. */
-#define INSN_ASE_MASK 0x3c00f000
-
-/* DSP ASE */
-#define INSN_DSP 0x00001000
-#define INSN_DSP64 0x00002000
-
-/* 0x00004000 is unused. */
-
-/* MIPS-3D ASE */
-#define INSN_MIPS3D 0x00008000
+/* MIPS R5900 instruction */
+#define INSN_5900 0x00004000
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
-/* MDMX ASE */
-#define INSN_MDMX 0x04000000
-/* MT ASE */
-#define INSN_MT 0x08000000
-/* SmartMIPS ASE */
-#define INSN_SMARTMIPS 0x10000000
-/* DSP R2 ASE */
-#define INSN_DSPR2 0x20000000
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
/* Loongson 3A. */
#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
-#define INSN_XLR 0x00000020
+#define INSN_XLR 0x00000020
+
+/* DSP ASE */
+#define ASE_DSP 0x00000001
+#define ASE_DSP64 0x00000002
+/* DSP R2 ASE */
+#define ASE_DSPR2 0x00000004
+/* Enhanced VA Scheme */
+#define ASE_EVA 0x00000008
+/* MCU (MicroController) ASE */
+#define ASE_MCU 0x00000010
+/* MDMX ASE */
+#define ASE_MDMX 0x00000020
+/* MIPS-3D ASE */
+#define ASE_MIPS3D 0x00000040
+/* MT ASE */
+#define ASE_MT 0x00000080
+/* SmartMIPS ASE */
+#define ASE_SMARTMIPS 0x00000100
+/* Virtualization ASE */
+#define ASE_VIRT 0x00000200
+#define ASE_VIRT64 0x00000400
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
+#define CPU_R5900 5900
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
#define CPU_LOONGSON_2F 3002
#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
+#define CPU_OCTEONP 6601
+#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */
+/* Return true if the given CPU is included in INSN_* mask MASK. */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+ switch (cpu)
+ {
+ case CPU_R4650:
+ case CPU_RM7000:
+ case CPU_RM9000:
+ return (mask & INSN_4650) != 0;
+
+ case CPU_R4010:
+ return (mask & INSN_4010) != 0;
+
+ case CPU_VR4100:
+ return (mask & INSN_4100) != 0;
+
+ case CPU_R3900:
+ return (mask & INSN_3900) != 0;
+
+ case CPU_R10000:
+ case CPU_R12000:
+ case CPU_R14000:
+ case CPU_R16000:
+ return (mask & INSN_10000) != 0;
+
+ case CPU_SB1:
+ return (mask & INSN_SB1) != 0;
+
+ case CPU_R4111:
+ return (mask & INSN_4111) != 0;
+
+ case CPU_VR4120:
+ return (mask & INSN_4120) != 0;
+
+ case CPU_VR5400:
+ return (mask & INSN_5400) != 0;
+
+ case CPU_VR5500:
+ return (mask & INSN_5500) != 0;
+
+ case CPU_R5900:
+ return (mask & INSN_5900) != 0;
+
+ case CPU_LOONGSON_2E:
+ return (mask & INSN_LOONGSON_2E) != 0;
+
+ case CPU_LOONGSON_2F:
+ return (mask & INSN_LOONGSON_2F) != 0;
+
+ case CPU_LOONGSON_3A:
+ return (mask & INSN_LOONGSON_3A) != 0;
+
+ case CPU_OCTEON:
+ return (mask & INSN_OCTEON) != 0;
+
+ case CPU_OCTEONP:
+ return (mask & INSN_OCTEONP) != 0;
+
+ case CPU_OCTEON2:
+ return (mask & INSN_OCTEON2) != 0;
+
+ case CPU_XLR:
+ return (mask & INSN_XLR) != 0;
+
+ default:
+ return FALSE;
+ }
+}
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
- test, or zero if no CPU specific ISA test is desired. */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu) \
- (((isa & INSN_ISA_MASK) != 0 \
- && ((insn)->membership & INSN_ISA_MASK) != 0 \
- && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
- (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
- || ((isa & ~INSN_ISA_MASK) \
- & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
- || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
- || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
- || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
- || cpu == CPU_R16000) \
- && ((insn)->membership & INSN_10000) != 0) \
- || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
- || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
- || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
- || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
- || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || (cpu == CPU_LOONGSON_2E \
- && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
- || (cpu == CPU_LOONGSON_2F \
- && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
- || (cpu == CPU_LOONGSON_3A \
- && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
- || (cpu == CPU_OCTEON \
- && ((insn)->membership & INSN_OCTEON) != 0) \
- || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
- || 0) /* Please keep this term for easier source merging. */
+ test, or zero if no CPU specific ISA test is desired. Return true
+ if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
+{
+ if (!cpu_is_member (cpu, insn->exclusions))
+ {
+ /* Test for ISA level compatibility. */
+ if ((isa & INSN_ISA_MASK) != 0
+ && (insn->membership & INSN_ISA_MASK) != 0
+ && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+ >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+ return TRUE;
+
+ /* Test for ASE compatibility. */
+ if ((ase & insn->ase) != 0)
+ return TRUE;
+
+ /* Test for processor-specific extensions. */
+ if (cpu_is_member (cpu, insn->membership))
+ return TRUE;
+ }
+ return FALSE;
+}
/* This is a list of macro expanded instructions.
enum
{
M_ABS,
+ M_ACLR_AB,
+ M_ACLR_OB,
M_ADD_I,
M_ADDU_I,
M_AND_I,
+ M_ASET_AB,
+ M_ASET_OB,
M_BALIGN,
M_BC1FL,
M_BC1TL,
M_BNEL_I,
M_CACHE_AB,
M_CACHE_OB,
+ M_CACHEE_AB,
+ M_CACHEE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_LA_AB,
M_LB_A,
M_LB_AB,
+ M_LBE_OB,
+ M_LBE_AB,
M_LBU_A,
M_LBU_AB,
+ M_LBUE_OB,
+ M_LBUE_AB,
M_LCA_AB,
M_LD_A,
M_LD_OB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC2_OB,
+ M_LQC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDL_OB,
M_LDR_OB,
M_LH_A,
M_LH_AB,
+ M_LHE_OB,
+ M_LHE_AB,
M_LHU_A,
M_LHU_AB,
+ M_LHUE_OB,
+ M_LHUE_AB,
M_LI,
M_LI_D,
M_LI_DD,
M_LL_OB,
M_LLD_AB,
M_LLD_OB,
+ M_LLE_AB,
+ M_LLE_OB,
+ M_LQ_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
+ M_LWE_OB,
+ M_LWE_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
M_LWL_A,
M_LWL_AB,
M_LWL_OB,
+ M_LWLE_AB,
+ M_LWLE_OB,
M_LWM_AB,
M_LWM_OB,
M_LWP_AB,
M_LWR_A,
M_LWR_AB,
M_LWR_OB,
+ M_LWRE_AB,
+ M_LWRE_OB,
M_LWU_AB,
M_LWU_OB,
M_MSGSND,
M_OR_I,
M_PREF_AB,
M_PREF_OB,
+ M_PREFE_AB,
+ M_PREFE_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAA_OB,
+ M_SAAD_AB,
+ M_SAAD_OB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
M_SCD_OB,
+ M_SCE_AB,
+ M_SCE_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC2_OB,
+ M_SQC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDL_OB,
M_SNE_I,
M_SB_A,
M_SB_AB,
+ M_SBE_OB,
+ M_SBE_AB,
M_SH_A,
M_SH_AB,
+ M_SHE_OB,
+ M_SHE_AB,
+ M_SQ_AB,
M_SW_A,
M_SW_AB,
+ M_SWE_OB,
+ M_SWE_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
M_SWL_A,
M_SWL_AB,
M_SWL_OB,
+ M_SWLE_AB,
+ M_SWLE_OB,
M_SWM_AB,
M_SWM_OB,
M_SWP_AB,
M_SWR_A,
M_SWR_AB,
M_SWR_OB,
+ M_SWRE_AB,
+ M_SWRE_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
/* The following flags have the same value for the mips16 opcode
table:
+
+ INSN_ISA3
+
INSN_UNCOND_BRANCH_DELAY
INSN_COND_BRANCH_DELAY
INSN_COND_BRANCH_LIKELY (never used)
INSN_WRITE_HI
INSN_WRITE_LO
INSN_TRAP
- INSN_ISA3
+ FP_D (never used)
*/
extern const struct mips_opcode mips16_opcodes[];
#define MICROMIPSOP_SH_SEL 11
#define MICROMIPSOP_MASK_OFFSET12 0xfff
#define MICROMIPSOP_SH_OFFSET12 0
+#define MICROMIPSOP_MASK_3BITPOS 0x7
+#define MICROMIPSOP_SH_3BITPOS 21
#define MICROMIPSOP_MASK_STYPE 0x1f
#define MICROMIPSOP_SH_STYPE 16
#define MICROMIPSOP_MASK_OFFSET10 0x3ff
#define MICROMIPSOP_MASK_IMMY 0x1ff
#define MICROMIPSOP_SH_IMMY 1
+/* MIPS DSP ASE */
+#define MICROMIPSOP_MASK_DSPACC 0x3
+#define MICROMIPSOP_SH_DSPACC 14
+#define MICROMIPSOP_MASK_DSPSFT 0x3f
+#define MICROMIPSOP_SH_DSPSFT 16
+#define MICROMIPSOP_MASK_SA3 0x7
+#define MICROMIPSOP_SH_SA3 13
+#define MICROMIPSOP_MASK_SA4 0xf
+#define MICROMIPSOP_SH_SA4 12
+#define MICROMIPSOP_MASK_IMM8 0xff
+#define MICROMIPSOP_SH_IMM8 13
+#define MICROMIPSOP_MASK_IMM10 0x3ff
+#define MICROMIPSOP_SH_IMM10 16
+#define MICROMIPSOP_MASK_WRDSP 0x3f
+#define MICROMIPSOP_SH_WRDSP 14
+#define MICROMIPSOP_MASK_BP 0x3
+#define MICROMIPSOP_SH_BP 14
+
/* Placeholders for fields that only exist in the traditional 32-bit
instruction encoding; see the comment above for details. */
#define MICROMIPSOP_MASK_CODE20 0
#define MICROMIPSOP_SH_VECBYTE 0
#define MICROMIPSOP_MASK_VECALIGN 0
#define MICROMIPSOP_SH_VECALIGN 0
-#define MICROMIPSOP_MASK_DSPACC 0
-#define MICROMIPSOP_SH_DSPACC 0
#define MICROMIPSOP_MASK_DSPACC_S 0
#define MICROMIPSOP_SH_DSPACC_S 0
-#define MICROMIPSOP_MASK_DSPSFT 0
-#define MICROMIPSOP_SH_DSPSFT 0
#define MICROMIPSOP_MASK_DSPSFT_7 0
#define MICROMIPSOP_SH_DSPSFT_7 0
-#define MICROMIPSOP_MASK_SA3 0
-#define MICROMIPSOP_SH_SA3 0
-#define MICROMIPSOP_MASK_SA4 0
-#define MICROMIPSOP_SH_SA4 0
-#define MICROMIPSOP_MASK_IMM8 0
-#define MICROMIPSOP_SH_IMM8 0
-#define MICROMIPSOP_MASK_IMM10 0
-#define MICROMIPSOP_SH_IMM10 0
-#define MICROMIPSOP_MASK_WRDSP 0
-#define MICROMIPSOP_SH_WRDSP 0
#define MICROMIPSOP_MASK_RDDSP 0
#define MICROMIPSOP_SH_RDDSP 0
-#define MICROMIPSOP_MASK_BP 0
-#define MICROMIPSOP_SH_BP 0
#define MICROMIPSOP_MASK_MT_U 0
#define MICROMIPSOP_SH_MT_U 0
#define MICROMIPSOP_MASK_MT_H 0
#define MICROMIPSOP_SH_FZ 0
#define MICROMIPSOP_MASK_FZ 0
+/* microMIPS Enhanced VA Scheme */
+#define MICROMIPSOP_SH_EVAOFFSET 0
+#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
+
/* These are the characters which may appears in the args field of a microMIPS
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32
(MICROMIPSOP_*_SHAMT)
+ "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
"|" 4-bit trap code (MICROMIPSOP_*_TRAP)
"~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
"a" 26-bit target address (MICROMIPSOP_*_TARGET)
"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
- "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
+ "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
- "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+ "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
Coprocessor instructions:
"E" 5-bit target register (MICROMIPSOP_*_RT)
- "G" 5-bit destination register (MICROMIPSOP_*_RD)
+ "G" 5-bit destination register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
"+D" combined destination register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only
"f" 32-bit floating point constant
"l" 32-bit floating point constant in .lit4
+ DSP ASE usage:
+ "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
+ "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
+ "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
+ "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
+ "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
+ "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
+ "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
+ "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
+ "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
+ "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
+
+ microMIPS Enhanced VA Scheme:
+ "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+
Other:
"()" parens surrounding optional value
"," separates operands
"m" start of microMIPS extension sequence
Characters used so far, for quick reference when adding more:
- "1234567890"
- "<>(),+.|~"
+ "12345678 0"
+ "<>(),+.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
- ""
+ "j"
""
"ABCDEFGHI"
""
projects / deliverable / binutils-gdb.git / blobdiff