opcode/

[deliverable/binutils-gdb.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index a94860f058913a5020337c72deb046089e2636c9..eb28d160f353a0ad26e718170b3fef9aeb6ba425 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -713,10 +713,11 @@ static const unsigned int mips_isa_table[] =
   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK           0xc3ff0c20
+#define INSN_CHIP_MASK           0xc3ff0e20
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON              0x00000800
+#define INSN_OCTEONP             0x00000200
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x3c00f010
@@ -823,6 +824,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_LOONGSON_2F 3002
 #define CPU_LOONGSON_3A 3003
 #define CPU_OCTEON     6501
+#define CPU_OCTEONP    6601
 #define CPU_XLR        887682          /* decimal 'XLR'   */
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
@@ -859,6 +861,8 @@ static const unsigned int mips_isa_table[] =
          && ((insn)->membership & INSN_LOONGSON_3A) != 0)               \
      || (cpu == CPU_OCTEON                                             \
         && ((insn)->membership & INSN_OCTEON) != 0)                    \
+     || (cpu == CPU_OCTEONP                                            \
+        && ((insn)->membership & INSN_OCTEONP) != 0)                   \
      || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
      || 0)     /* Please keep this term for easier source merging.  */
 
@@ -1065,6 +1069,10 @@ enum
   M_S_DOB,
   M_S_DAB,
   M_S_S,
+  M_SAA_AB,
+  M_SAA_OB,
+  M_SAAD_AB,
+  M_SAAD_OB,
   M_SC_AB,
   M_SC_OB,
   M_SCD_AB,