/* Opcode table for the TI MSP430 microcontrollers
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2020 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This program is free software; you can redistribute it and/or modify
#ifndef __MSP430_H_
#define __MSP430_H_
+enum msp430_expp_e
+{
+ MSP_EXPP_ALL = 0, /* Use full the value of the expression - default. */
+ MSP_EXPP_LO, /* Extract least significant word from expression. */
+ MSP_EXPP_HI, /* Extract 2nd word from expression. */
+ MSP_EXPP_LLO, /* Extract least significant word from an
+ immediate value. */
+ MSP_EXPP_LHI, /* Extract 2nd word from an immediate value. */
+ MSP_EXPP_HLO, /* Extract 3rd word from an immediate value. */
+ MSP_EXPP_HHI, /* Extract 4th word from an immediate value. */
+};
+
struct msp430_operand_s
{
int ol; /* Operand length words. */
int reg; /* Register. */
int mode; /* Operand mode. */
int vshift; /* Number of bytes to shift operand down. */
+ enum msp430_expp_e expp; /* For when the operand is a constant
+ expression, the part of the expression to
+ extract. */
#define OP_REG 0
#define OP_EXP 1
#ifndef DASM_SECTION
#endif
};
-#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
+/* Byte operation flag for all instructions. Also used as the
+ A/L bit in the extension word to indicate a 20-bit operation. */
+#define BYTE_OPERATION (1 << 6)
+/* Z/C bit in the extension word. If set the carry bit is ignored
+ for the duration of the operation, although it may be changed as
+ a result of the operation. */
+#define IGNORE_CARRY_BIT (1 << 8)
struct msp430_opcode_s
{
- char *name;
+ const char *name;
int fmt;
int insn_opnumb;
int bin_opcode;
int bin_mask;
};
-#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
+#define MSP_INSN(name, fmt, numb, bin, mask) { #name, fmt, numb, bin, mask }
static struct msp430_opcode_s msp430_opcodes[] =
{
MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
MSP_INSN (rrax, -3, 1, 0x1100, 0xff80),
- MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80),
+ MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit clear. */
+ MSP_INSN (rrux, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit set. */
MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0),
MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0),
MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0),
- MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */
-
MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0),
MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0),
MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0),