/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Copyright (C) 1994-2015 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
+extern const struct powerpc_opcode vle_opcodes[];
+extern const int vle_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
#define PPC_OPCODE_POWER2 4
-/* Opcode is only defined on 32 bit architectures. */
-#define PPC_OPCODE_32 8
-
-/* Opcode is only defined on 64 bit architectures. */
-#define PPC_OPCODE_64 0x10
-
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */
-#define PPC_OPCODE_601 0x20
+#define PPC_OPCODE_601 8
/* Opcode is supported in both the Power and PowerPC architectures
- (ie, compiler's -mcpu=common or assembler's -mcom). */
-#define PPC_OPCODE_COMMON 0x40
+ (ie, compiler's -mcpu=common or assembler's -mcom). More than just
+ the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
+ and PPC_OPCODE_POWER2 because many instructions changed mnemonics
+ between POWER and POWERPC. */
+#define PPC_OPCODE_COMMON 0x10
/* Opcode is supported for any Power or PowerPC platform (this is
for the assembler's -many option, and it eliminates duplicates). */
-#define PPC_OPCODE_ANY 0x80
+#define PPC_OPCODE_ANY 0x20
+
+/* Opcode is only defined on 64 bit architectures. */
+#define PPC_OPCODE_64 0x40
/* Opcode is supported as part of the 64-bit bridge. */
-#define PPC_OPCODE_64_BRIDGE 0x100
+#define PPC_OPCODE_64_BRIDGE 0x80
/* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC 0x200
+#define PPC_OPCODE_ALTIVEC 0x100
/* Opcode is supported by PowerPC 403 processor. */
-#define PPC_OPCODE_403 0x400
+#define PPC_OPCODE_403 0x200
/* Opcode is supported by PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE 0x800
-
-/* Opcode is only supported by 64-bit PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE64 0x1000
+#define PPC_OPCODE_BOOKE 0x400
/* Opcode is supported by PowerPC 440 processor. */
-#define PPC_OPCODE_440 0x2000
+#define PPC_OPCODE_440 0x800
/* Opcode is only supported by Power4 architecture. */
-#define PPC_OPCODE_POWER4 0x4000
+#define PPC_OPCODE_POWER4 0x1000
/* Opcode is only supported by Power7 architecture. */
-#define PPC_OPCODE_POWER7 0x8000
-
-/* Opcode is only supported by POWERPC Classic architecture. */
-#define PPC_OPCODE_CLASSIC 0x10000
+#define PPC_OPCODE_POWER7 0x2000
/* Opcode is only supported by e500x2 Core. */
-#define PPC_OPCODE_SPE 0x20000
+#define PPC_OPCODE_SPE 0x4000
/* Opcode is supported by e500x2 Integer select APU. */
-#define PPC_OPCODE_ISEL 0x40000
+#define PPC_OPCODE_ISEL 0x8000
/* Opcode is an e500 SPE floating point instruction. */
-#define PPC_OPCODE_EFS 0x80000
+#define PPC_OPCODE_EFS 0x10000
/* Opcode is supported by branch locking APU. */
-#define PPC_OPCODE_BRLOCK 0x100000
+#define PPC_OPCODE_BRLOCK 0x20000
/* Opcode is supported by performance monitor APU. */
-#define PPC_OPCODE_PMR 0x200000
+#define PPC_OPCODE_PMR 0x40000
/* Opcode is supported by cache locking APU. */
-#define PPC_OPCODE_CACHELCK 0x400000
+#define PPC_OPCODE_CACHELCK 0x80000
/* Opcode is supported by machine check APU. */
-#define PPC_OPCODE_RFMCI 0x800000
+#define PPC_OPCODE_RFMCI 0x100000
/* Opcode is only supported by Power5 architecture. */
-#define PPC_OPCODE_POWER5 0x1000000
+#define PPC_OPCODE_POWER5 0x200000
/* Opcode is supported by PowerPC e300 family. */
-#define PPC_OPCODE_E300 0x2000000
+#define PPC_OPCODE_E300 0x400000
/* Opcode is only supported by Power6 architecture. */
-#define PPC_OPCODE_POWER6 0x4000000
+#define PPC_OPCODE_POWER6 0x800000
/* Opcode is only supported by PowerPC Cell family. */
-#define PPC_OPCODE_CELL 0x8000000
+#define PPC_OPCODE_CELL 0x1000000
/* Opcode is supported by CPUs with paired singles support. */
-#define PPC_OPCODE_PPCPS 0x10000000
+#define PPC_OPCODE_PPCPS 0x2000000
/* Opcode is supported by Power E500MC */
-#define PPC_OPCODE_E500MC 0x20000000
+#define PPC_OPCODE_E500MC 0x4000000
/* Opcode is supported by PowerPC 405 processor. */
-#define PPC_OPCODE_405 0x40000000
+#define PPC_OPCODE_405 0x8000000
/* Opcode is supported by Vector-Scalar (VSX) Unit */
-#define PPC_OPCODE_VSX 0x80000000
+#define PPC_OPCODE_VSX 0x10000000
/* Opcode is supported by A2. */
-#define PPC_OPCODE_A2 0x100000000ULL
+#define PPC_OPCODE_A2 0x20000000
/* Opcode is supported by PowerPC 476 processor. */
-#define PPC_OPCODE_476 0x200000000ULL
+#define PPC_OPCODE_476 0x40000000
/* Opcode is supported by AppliedMicro Titan core */
-#define PPC_OPCODE_TITAN 0x400000000ULL
+#define PPC_OPCODE_TITAN 0x80000000
/* Opcode which is supported by the e500 family */
-#define PPC_OPCODE_E500 0x800000000ULL
+#define PPC_OPCODE_E500 0x100000000ull
+
+/* Opcode is supported by Extended Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC2 0x200000000ull
+
+/* Opcode is supported by Power E6500 */
+#define PPC_OPCODE_E6500 0x400000000ull
+
+/* Opcode is supported by Thread management APU */
+#define PPC_OPCODE_TMR 0x800000000ull
+
+/* Opcode which is supported by the VLE extension. */
+#define PPC_OPCODE_VLE 0x1000000000ull
+
+/* Opcode is only supported by Power8 architecture. */
+#define PPC_OPCODE_POWER8 0x2000000000ull
+
+/* Opcode which is supported by the Hardware Transactional Memory extension. */
+/* Currently, this is the same as the POWER8 mask. If another cpu comes out
+ that isn't a superset of POWER8, we can define this to its own mask. */
+#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
+
+/* Opcode is supported by ppc750cl. */
+#define PPC_OPCODE_750 0x4000000000ull
+
+/* Opcode is supported by ppc7450. */
+#define PPC_OPCODE_7450 0x8000000000ull
+
+/* Opcode is supported by ppc821/850/860. */
+#define PPC_OPCODE_860 0x10000000000ull
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn. */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
+
+/* A macro to extract the major opcode from a VLE instruction. */
+#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
+
+/* A macro to convert a VLE opcode to a VLE opcode segment. */
+#define VLE_OP_TO_SEG(i) ((i) >> 1)
\f
/* The operands table is an array of struct powerpc_operand. */
/* A bitmask of bits in the operand. */
unsigned int bitm;
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
+ /* The shift operation to be applied to the operand. No shift
+ is made if this is zero. For positive values, the operand
+ is shifted left by SHIFT. For negative values, the operand
+ is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
+ that BITM and SHIFT cannot be used to determine where the
+ operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
+ if (o->shift >= 0)
+ i |= (op & o->bitm) << o->shift;
+ else
+ i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
extract this operand type from an instruction, check this field.
If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
+ if (o->shift >= 0)
+ op = (i >> o->shift) & o->bitm;
+ else
+ op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
+/* Use with the shift field of a struct powerpc_operand to indicate
+ that BITM and SHIFT cannot be used to determine where the operand
+ goes in the insn. */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
+#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names. */
+#define PPC_OPERAND_CR_REG (0x200000)
+
+/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
+ is omitted, then the value it should use for the operand is stored
+ in the SHIFT field of the immediatly following operand field. */
+#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
\f
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
-extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
+extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
+
+static inline long
+ppc_optional_operand_value (const struct powerpc_operand *operand)
+{
+ if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
+ return (operand+1)->shift;
+ return 0;
+}
#endif /* PPC_H */
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