/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1999, 2000, 2001, 2002
+ Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef PPC_H
#define PPC_H
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
- char operands[8];
+ unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 (020)
+/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
+ is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
+ but it also supports many additional POWER instructions. */
+#define PPC_OPCODE_601 (040)
+
+/* Opcode is supported in both the Power and PowerPC architectures
+ (ie, compiler's -mcpu=common or assembler's -mcom). */
+#define PPC_OPCODE_COMMON (0100)
+
+/* Opcode is supported for any Power or PowerPC platform (this is
+ for the assembler's -many option, and it eliminates duplicates). */
+#define PPC_OPCODE_ANY (0200)
+
+/* Opcode is supported as part of the 64-bit bridge. */
+#define PPC_OPCODE_64_BRIDGE (0400)
+
+/* Opcode is supported by Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC (01000)
+
+/* Opcode is supported by PowerPC 403 processor. */
+#define PPC_OPCODE_403 (02000)
+
+/* Opcode is supported by PowerPC BookE processor. */
+#define PPC_OPCODE_BOOKE (04000)
+
+/* Opcode is only supported by 64-bit PowerPC BookE processor. */
+#define PPC_OPCODE_BOOKE64 (010000)
+
+/* Opcode is only supported by Power4 architecture. */
+#define PPC_OPCODE_POWER4 (020000)
+
+/* Opcode isn't supported by Power4 architecture. */
+#define PPC_OPCODE_NOPOWER4 (040000)
+
+/* Opcode is only supported by POWERPC Classic architecture. */
+#define PPC_OPCODE_CLASSIC (0100000)
+
+/* Opcode is only supported by e500x2 Core. */
+#define PPC_OPCODE_SPE (0200000)
+
+/* Opcode is supported by e500x2 Integer select APU. */
+#define PPC_OPCODE_ISEL (0400000)
+
+/* Opcode is an e500 SPE floating point instruction. */
+#define PPC_OPCODE_EFS (01000000)
+
+/* Opcode is supported by branch locking APU. */
+#define PPC_OPCODE_BRLOCK (02000000)
+
+/* Opcode is supported by performance monitor APU. */
+#define PPC_OPCODE_PMR (04000000)
+
+/* Opcode is supported by cache locking APU. */
+#define PPC_OPCODE_CACHELCK (010000000)
+
+/* Opcode is supported by machine check APU. */
+#define PPC_OPCODE_RFMCI (020000000)
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
\f
/* How far the operand is left shifted in the instruction. */
int shift;
- /* Non zero if the operand is signed (this is zero for most
- operands). */
- int signedp;
-
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
+ int dialect,
const char **errmsg));
/* Extraction function. This is used by the disassembler. To
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
- if (o->signedp
+ if ((o->flags & PPC_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
- long (*extract) PARAMS ((unsigned long instruction, int *invalid));
+ long (*extract) PARAMS ((unsigned long instruction, int dialect,
+ int *invalid));
/* One bit syntax flags. */
unsigned long flags;
/* Values defined for the flags field of a struct powerpc_operand. */
+/* This operand takes signed values. */
+#define PPC_OPERAND_SIGNED (01)
+
+/* This operand takes signed values, but also accepts a full positive
+ range of values when running in 32 bit mode. That is, if bits is
+ 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
+ this flag is ignored. */
+#define PPC_OPERAND_SIGNOPT (02)
+
/* This operand does not actually exist in the assembler input. This
is used to support extended mnemonics such as mr, for which two
operands fields are identical. The assembler should call the
insert function with any op value. The disassembler should call
the extract function, ignore the return value, and check the value
placed in the valid argument. */
-#define PPC_OPERAND_FAKE (01)
+#define PPC_OPERAND_FAKE (04)
/* The next operand should be wrapped in parentheses rather than
separated from this one by a comma. This is used for the load and
store instructions which want their operands to look like
reg,displacement(reg)
*/
-#define PPC_OPERAND_PARENS (02)
+#define PPC_OPERAND_PARENS (010)
/* This operand may use the symbolic names for the CR fields, which
are
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (04)
+#define PPC_OPERAND_CR (020)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
-#define PPC_OPERAND_GPR (010)
+#define PPC_OPERAND_GPR (040)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
-#define PPC_OPERAND_FPR (020)
+#define PPC_OPERAND_FPR (0100)
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
-#define PPC_OPERAND_RELATIVE (0100)
+#define PPC_OPERAND_RELATIVE (0200)
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
-#define PPC_OPERAND_ABSOLUTE (0200)
+#define PPC_OPERAND_ABSOLUTE (0400)
/* This operand is optional, and is zero if omitted. This is used for
the optional BF and L fields in the comparison instructions. The
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
-#define PPC_OPERAND_OPTIONAL (0400)
+#define PPC_OPERAND_OPTIONAL (01000)
/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
is omitted, then for the next operand use this operand value plus
hack is needed because the Power rotate instructions can take
either 4 or 5 operands. The disassembler should print this operand
out regardless of the PPC_OPERAND_OPTIONAL field. */
-#define PPC_OPERAND_NEXT (01000)
+#define PPC_OPERAND_NEXT (02000)
/* This operand should be regarded as a negative number for the
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
-#define PPC_OPERAND_NEGATIVE (02000)
+#define PPC_OPERAND_NEGATIVE (04000)
+
+/* This operand names a vector unit register. The disassembler
+ prints these with a leading 'v'. */
+#define PPC_OPERAND_VR (010000)
+
+/* This operand is for the DS field in a DS form instruction. */
+#define PPC_OPERAND_DS (020000)
\f
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
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