2003-01-07 Chris Demetriou <cgd@broadcom.com>

[deliverable/binutils-gdb.git] / include / opcode / ppc.h

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index c313696c6fe0bce4b92abf5161731cc0aa12e60f..ffd313acd527486c99c2c01b15d1f86a1def04ae 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -1,5 +1,6 @@
 /* ppc.h -- Header file for PowerPC opcode table
-   Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002
+   Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -94,12 +95,42 @@ extern const int powerpc_num_opcodes;
 /* Opcode is supported by PowerPC 403 processor.  */
 #define PPC_OPCODE_403 (02000)
 
-/* Opcode is supported by Motorola BookE processor.  */
+/* Opcode is supported by PowerPC BookE processor.  */
 #define PPC_OPCODE_BOOKE (04000)
 
-/* Opcode is only supported by 64-bit Motorola BookE processor.  */
+/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 #define PPC_OPCODE_BOOKE64 (010000)
 
+/* Opcode is only supported by Power4 architecture.  */
+#define PPC_OPCODE_POWER4 (020000)
+
+/* Opcode isn't supported by Power4 architecture.  */
+#define PPC_OPCODE_NOPOWER4 (040000)
+
+/* Opcode is only supported by POWERPC Classic architecture.  */
+#define PPC_OPCODE_CLASSIC (0100000)
+
+/* Opcode is only supported by e500x2 Core.  */
+#define PPC_OPCODE_SPE     (0200000)
+
+/* Opcode is supported by e500x2 Integer select APU.  */
+#define PPC_OPCODE_ISEL     (0400000)
+
+/* Opcode is an e500 SPE floating point instruction.  */
+#define PPC_OPCODE_EFS      (01000000)
+
+/* Opcode is supported by branch locking APU.  */
+#define PPC_OPCODE_BRLOCK   (02000000)
+
+/* Opcode is supported by performance monitor APU.  */
+#define PPC_OPCODE_PMR      (04000000)
+
+/* Opcode is supported by cache locking APU.  */
+#define PPC_OPCODE_CACHELCK (010000000)
+
+/* Opcode is supported by machine check APU.  */
+#define PPC_OPCODE_RFMCI    (020000000)
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 \f
@@ -130,6 +161,7 @@ struct powerpc_operand
      operand value is legal, *ERRMSG will be unchanged (most operands
      can accept any value).  */
   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
+                                  int dialect,
                                   const char **errmsg));
 
   /* Extraction function.  This is used by the disassembler.  To
@@ -149,7 +181,8 @@ struct powerpc_operand
      non-zero if this operand type can not actually be extracted from
      this operand (i.e., the instruction does not match).  If the
      operand is valid, *INVALID will not be changed.  */
-  long (*extract) PARAMS ((unsigned long instruction, int *invalid));
+  long (*extract) PARAMS ((unsigned long instruction, int dialect,
+                          int *invalid));
 
   /* One bit syntax flags.  */
   unsigned long flags;