/* Opcode decoder for the Renesas RL78
- Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
Written by DJ Delorie <dj@redhat.com>
This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
#ifndef RL78_OPCODES_H_INCLUDED
#define RL78_OPCODES_H_INCLUDED
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ RL78_ISA_DEFAULT,
+ RL78_ISA_G10,
+ RL78_ISA_G13,
+ RL78_ISA_G14,
+} RL78_Dis_Isa;
+
/* For the purposes of these structures, the RL78 registers are as
follows, despite most of these being memory-mapped and
bank-switched: */
RL78_Opcode_Operand op[2];
} RL78_Opcode_Decoded;
-int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
+int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa);
+
+#ifdef __cplusplus
+}
+#endif
#endif