-/* to sanitize this file, grep -v v9 < sparc.h > clean-sparc.h */
-
/* Definitions for opcode table for the sparc.
- Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
-
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+#include "ansidecl.h"
/* The SPARC opcode table (and other related data) is defined in
- the BFD library in opc-sparc.c. If you change anything here, make
+ the opcodes library in sparc-opc.c. If you change anything here, make
sure you fix up that file, and vice versa. */
/* FIXME-someday: perhaps the ,a's and such should be embedded in the
instruction's name rather than the args. This would make gas faster, pinsn
slower, but would mess up some macros a bit. xoxorich. */
-#if !defined(__STDC__) && !defined(const)
-#define const
-#endif
+/* List of instruction sets variations.
+ These values are such that each element is either a superset of a
+ preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
+ returns non-zero.
+ The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
+ Don't change this without updating sparc-opc.c. */
+
+enum sparc_opcode_arch_val {
+ SPARC_OPCODE_ARCH_V6 = 0,
+ SPARC_OPCODE_ARCH_V7,
+ SPARC_OPCODE_ARCH_V8,
+ SPARC_OPCODE_ARCH_SPARCLET,
+ SPARC_OPCODE_ARCH_SPARCLITE,
+ /* v9 variants must appear last */
+ SPARC_OPCODE_ARCH_V9,
+ SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
+ SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
+ SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
+};
-#define sparc_architecture bfd_sparc_architecture
-#define architecture_pname bfd_sparc_architecture_pname
-#define sparc_opcode bfd_sparc_opcode
-#define sparc_opcodes bfd_sparc_opcodes
+/* The highest architecture in the table. */
+#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
-/*
- * Structure of an opcode table entry.
- * This enumerator must parallel the architecture_pname array
- * in bfd/opc-sparc.c.
- */
-enum sparc_architecture {
- v6 = 0,
- v7,
- v8,
- sparclite,
- v9
+/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
+ insn encoding/decoding. */
+#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
+
+/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
+#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
+
+/* Table of cpu variants. */
+
+struct sparc_opcode_arch {
+ const char *name;
+ /* Mask of sparc_opcode_arch_val's supported.
+ EG: For v7 this would be
+ (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
+ These are short's because sparc_opcode.architecture is. */
+ short supported;
};
-extern const char *architecture_pname[];
+extern const struct sparc_opcode_arch sparc_opcode_archs[];
-/* Sparclite and v9 are both supersets of v8; we can't bump between them. */
+/* Given architecture name, look up it's sparc_opcode_arch_val value. */
+extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
+ PARAMS ((const char *));
-#define ARCHITECTURES_CONFLICT_P(ARCH1, ARCH2) ((ARCH1) == sparclite && (ARCH2) == v9)
+/* Return the bitmask of supported architectures for ARCH. */
+#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
+
+/* Non-zero if ARCH1 conflicts with ARCH2.
+ IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
+#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
+(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
+ != SPARC_OPCODE_SUPPORTED (ARCH1)) \
+ && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
+ != SPARC_OPCODE_SUPPORTED (ARCH2)))
+
+/* Structure of an opcode table entry. */
struct sparc_opcode {
- const char *name;
- unsigned long match; /* Bits that must be set. */
- unsigned long lose; /* Bits that must not be set. */
- const char *args;
- /* This was called "delayed" in versions before the flags. */
- char flags;
- enum sparc_architecture architecture;
+ const char *name;
+ unsigned long match; /* Bits that must be set. */
+ unsigned long lose; /* Bits that must not be set. */
+ const char *args;
+ /* This was called "delayed" in versions before the flags. */
+ char flags;
+ short architecture; /* Bitmask of sparc_opcode_arch_val's. */
};
#define F_DELAYED 1 /* Delayed branch */
#define F_ALIAS 2 /* Alias for a "real" instruction */
+#define F_UNBR 4 /* Unconditional branch */
+#define F_CONDBR 8 /* Conditional branch */
+#define F_JSR 16 /* Subroutine call */
+#define F_FLOAT 32 /* Floating point instruction (not a branch) */
+#define F_FBR 64 /* Floating point branch */
+/* FIXME: Add F_ANACHRONISTIC flag for v9. */
/*
f frs2 floating point register.
B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4).
- j frs3 floating point register. (v9)
- u frs3 floating point register. (double/even) (v9)
- U frs3 floating point register. (quad/multiple of 4) (v9)
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
m alternate space register (asr) in rd
M alternate space register (asr) in rs1
h 22 high bits.
- K MEMBAR mask (4 bits). (v9)
+ X 5 bit unsigned immediate
+ Y 6 bit unsigned immediate
+ 3 SIAM mode (3 bits). (v9b)
+ K MEMBAR mask (7 bits). (v9)
+ j 10 bit Immediate. (v9)
I 11 bit Immediate. (v9)
i 13 bit Immediate.
n 22 bit immediate.
p Processor state register.
N Branch predict clear ",pn" (v9)
T Branch predict set ",pt" (v9)
- z icc. (v9)
- Z xcc. (v9)
+ z %icc. (v9)
+ Z %xcc. (v9)
q Floating point queue.
- r Single register that is both rs1 and rsd.
+ r Single register that is both rs1 and rd.
+ O Single register that is both rs2 and rd.
Q Coprocessor queue.
S Special case.
t Trap base register.
w Window invalid mask register.
y Y register.
- Y %amr (v9?)
+ u sparclet coprocessor registers in rd position
+ U sparclet coprocessor registers in rs1 position
+ E %ccr. (v9)
+ s %fprs. (v9)
P %pc. (v9)
- E %modes. (v9)
W %tick. (v9)
- s %usr. (v9)
o %asi. (v9)
- 6 fcc0. (v9)
- 7 fcc1. (v9)
- 8 fcc2. (v9)
- 9 fcc3. (v9)
+ 6 %fcc0. (v9)
+ 7 %fcc1. (v9)
+ 8 %fcc2. (v9)
+ 9 %fcc3. (v9)
! Privileged Register in rd (v9)
? Privileged Register in rs1 (v9)
+ * Prefetch function constant. (v9)
+ x OPF field (v9 impdep).
+ 0 32/64 bit immediate for set or setx (v9) insns
+ _ Ancillary state register in rd (v9a)
+ / Ancillary state register in rs1 (v9a)
The following chars are unused: (note: ,[] are used as punctuation)
-[osxOX3450]
+[45]
*/
#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
-#define OPF_LOW(x) OPF((x)&0xf) /* v9 */
+#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
#define RD(x) (((x)&0x1f) << 25) /* destination register field */
#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
#define ASI_RS2(x) (SIMM13(x))
+#define MEMBAR(x) ((x)&0x7f)
+#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
#define ANNUL (1<<29)
#define BPRED (1<<19) /* v9 */
#define RS1_G0 RS1(~0)
#define RS2_G0 RS2(~0)
-extern struct sparc_opcode sparc_opcodes[];
-extern const int bfd_sparc_num_opcodes;
-
-#define NUMOPCODES bfd_sparc_num_opcodes
+extern const struct sparc_opcode sparc_opcodes[];
+extern const int sparc_num_opcodes;
+
+extern int sparc_encode_asi PARAMS ((const char *));
+extern const char *sparc_decode_asi PARAMS ((int));
+extern int sparc_encode_membar PARAMS ((const char *));
+extern const char *sparc_decode_membar PARAMS ((int));
+extern int sparc_encode_prefetch PARAMS ((const char *));
+extern const char *sparc_decode_prefetch PARAMS ((int));
+extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));
+extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));
/*
* Local Variables:
projects / deliverable / binutils-gdb.git / blobdiff