/* Definitions for opcode table for the sparc.
- Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997
+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-#include <ansidecl.h>
+#include "ansidecl.h"
/* The SPARC opcode table (and other related data) is defined in
the opcodes library in sparc-opc.c. If you change anything here, make
/* v9 variants must appear last */
SPARC_OPCODE_ARCH_V9,
SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
+ SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
};
extern const struct sparc_opcode_arch sparc_opcode_archs[];
/* Given architecture name, look up it's sparc_opcode_arch_val value. */
-extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch ();
+extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
+ PARAMS ((const char *));
/* Return the bitmask of supported architectures for ARCH. */
#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
h 22 high bits.
X 5 bit unsigned immediate
Y 6 bit unsigned immediate
+ 3 SIAM mode (3 bits). (v9b)
K MEMBAR mask (7 bits). (v9)
j 10 bit Immediate. (v9)
I 11 bit Immediate. (v9)
* Prefetch function constant. (v9)
x OPF field (v9 impdep).
0 32/64 bit immediate for set or setx (v9) insns
+ _ Ancillary state register in rd (v9a)
+ / Ancillary state register in rs1 (v9a)
The following chars are unused: (note: ,[] are used as punctuation)
-[345]
+[45]
*/
#define RS1_G0 RS1(~0)
#define RS2_G0 RS2(~0)
-extern struct sparc_opcode sparc_opcodes[];
+extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;
extern int sparc_encode_asi PARAMS ((const char *));