Ensure 8-byte alignment for AArch64 stubs.

[deliverable/binutils-gdb.git] / ld / testsuite / ld-aarch64 / erratum843419.d

diff --git a/ld/testsuite/ld-aarch64/erratum843419.d b/ld/testsuite/ld-aarch64/erratum843419.d
index f0934f02e21467a8fd78e9968c584e99b466a891..7adfafde95a4c7b8cdb1d24791a26c4e8e006ead 100644 (file)
--- a/ld/testsuite/ld-aarch64/erratum843419.d
+++ b/ld/testsuite/ld-aarch64/erratum843419.d
@@ -17,23 +17,24 @@ Disassembly of section .e843419:
 [ ]*20000ff8:  90100000        adrp    x0, 40000000 <[_a-zA-Z0-9]+>
 [ ]*20000ffc:  f800c007        stur    x7, \[x0, #12\]
 [ ]*20001000:  d2800128        mov     x8, #0x9                        // #9
-[ ]*20001004:  14000008        b       20001024 <e843419@0002_00000013_1004>
+[ ]*20001004:  14000009        b       20001028 <e843419@0002_00000013_1004>
 [ ]*20001008:  8b050020        add     x0, x1, x5
 [ ]*2000100c:  b9400fe7        ldr     w7, \[sp, #12\]
 [ ]*20001010:  0b0700e0        add     w0, w7, w7
 [ ]*20001014:  910043ff        add     sp, sp, #0x10
-[ ]*20001018:  14000005        b       2000102c <__e835769_veneer>
+[ ]*20001018:  14000006        b       20001030 <__e835769_veneer>
 [ ]*2000101c:  d65f03c0        ret
-[ ]*20001020:  14000400        b       20002020 <__e835769_veneer\+0xff4>
+[ ]*20001020:  14000400        b       20002020 <__e835769_veneer\+0xff0>
+[ ]*20001024:  d503201f        nop
 
-0*20001024 <e843419@0002_00000013_1004>:
-[ ]*20001024:  f9000008        str     x8, \[x0\]
-[ ]*20001028:  17fffff8        b       20001008 <e843419_1\+0x10>
+0*20001028 <e843419@0002_00000013_1004>:
+[ ]*20001028:  f9000008        str     x8, \[x0\]
+[ ]*2000102c:  17fffff7        b       20001008 <e843419_1\+0x10>
 
-0*2000102c <__e835769_veneer>:
-[ ]*2000102c:  f0f17ff0        adrp    x16, 3000000 <e835769>
-[ ]*20001030:  91000210        add     x16, x16, #0x0
-[ ]*20001034:  d61f0200        br      x16
+0*20001030 <__e835769_veneer>:
+[ ]*20001030:  f0f17ff0        adrp    x16, 3000000 <e835769>
+[ ]*20001034:  91000210        add     x16, x16, #0x0
+[ ]*20001038:  d61f0200        br      x16
        ...
 
 Disassembly of section .e835769:
@@ -42,14 +43,15 @@ Disassembly of section .e835769:
 [ ]*3000000:   b8408c87        ldr     w7, \[x4, #8\]!
 [ ]*3000004:   1b017c06        mul     w6, w0, w1
 [ ]*3000008:   f9400084        ldr     x4, \[x4\]
-[ ]*300000c:   14000004        b       300001c <__erratum_835769_veneer_0>
+[ ]*300000c:   14000005        b       3000020 <__erratum_835769_veneer_0>
 [ ]*3000010:   aa0503e0        mov     x0, x5
 [ ]*3000014:   d65f03c0        ret
-[ ]*3000018:   14000400        b       3001018 <__erratum_835769_veneer_0\+0xffc>
+[ ]*3000018:   14000400        b       3001018 <__erratum_835769_veneer_0\+0xff8>
+[ ]*300001c:   d503201f        nop
 
-0*300001c <__erratum_835769_veneer_0>:
-[ ]*300001c:   9b031845        madd    x5, x2, x3, x6
-[ ]*3000020:   17fffffc        b       3000010 <e835769\+0x10>
+0*3000020 <__erratum_835769_veneer_0>:
+[ ]*3000020:   9b031845        madd    x5, x2, x3, x6
+[ ]*3000024:   17fffffb        b       3000010 <e835769\+0x10>
        ...
 
 Disassembly of section .text:
@@ -58,12 +60,14 @@ Disassembly of section .text:
 [ ]*400000:    d10043ff        sub     sp, sp, #0x10
 [ ]*400004:    d28001a7        mov     x7, #0xd                        // #13
 [ ]*400008:    b9000fe7        str     w7, \[sp, #12\]
-[ ]*40000c:    14000003        b       400018 <__e843419_veneer>
+[ ]*40000c:    14000005        b       400020 <__e843419_veneer>
 [ ]*400010:    d65f03c0        ret
-[ ]*400014:    14000400        b       401014 <__e843419_veneer\+0xffc>
+[ ]*400014:    d503201f        nop
+[ ]*400018:    14000400        b       401018 <__e843419_veneer\+0xff8>
+[ ]*40001c:    d503201f        nop
 
-0*400018 <__e843419_veneer>:
-[ ]*400018:    900fe010        adrp    x16, 20000000 <e843419>
-[ ]*40001c:    91000210        add     x16, x16, #0x0
-[ ]*400020:    d61f0200        br      x16
+0*400020 <__e843419_veneer>:
+[ ]*400020:    900fe010        adrp    x16, 20000000 <e843419>
+[ ]*400024:    91000210        add     x16, x16, #0x0
+[ ]*400028:    d61f0200        br      x16
        ...