-2012-11-30 Oleg Raikhman <oleg@adapteva.com>
- Joern Rennecke <joern.rennecke@embecosm.com>
-
- * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
-
-2012-11-29 Roland McGrath <mcgrathr@google.com>
-
- * s390-mkopc.c (file_header): Add const.
-
-2012-11-29 David Holsgrove <david.holsgrove@xilinx.com>
-
- * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
- INST_TYPE_R1_R2_SPECIAL
- * microblaze-dis.c (print_insn_microblaze): Same.
-
-2012-11-23 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
- set from ppc_opts.sticky in it. Delete "retain_mask".
- (powerpc_init_dialect): Choose default dialect from info->mach
- before parsing -M options. Handle more bfd_mach_ppc variants.
- Update common default to power7.
+2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
+ VCLIPW.
+
+2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
+ Konrad Eisele <konrad@gaisler.com>
+
+ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
+ bfd_mach_sparc.
+ * sparc-opc.c (MASK_LEON): Define.
+ (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
+ (letandleon): New macro.
+ (v9andleon): Likewise.
+ (sparc_opc): Add leon.
+ (umac): Enable for letandleon.
+ (smac): Likewise.
+ (casa): Enable for v9andleon.
+ (cas): Likewise.
+ (casl): Likewise.
+
+2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
+ OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
+ (print_vu0_channel): New function.
+ (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
+ (print_insn_args): Handle '#'.
+ (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
+ * mips-opc.c (mips_vu0_channel_mask): New constant.
+ (decode_mips_operand): Handle new VU0 operand types.
+ (VU0, VU0CH): New macros.
+ (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
+ for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
+ Use "+6" rather than "G" for QMFC2 and QMTC2.
+
+2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-formats.h (PCREL): Reorder parameters and update the definition
+ to match new mips_pcrel_operand layout.
+ (JUMP, JALX, BRANCH): Update accordingly.
+ * mips16-opc.c (decode_mips16_operand): Likewise.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * micromips-opc.c (WR_s): Delete.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
+ New macros.
+ (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
+ (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
+ (mips_builtin_opcodes): Use the new position-based read-write flags
+ instead of field-based ones. Use UDI for "udi..." instructions.
+ * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+ New macros.
+ (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
+ (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
+ (WR_SP, RD_16): New macros.
+ (RD_SP): Redefine as an INSN2_* flag.
+ (MOD_SP): Redefine in terms of RD_SP and WR_SP.
+ (mips16_opcodes): Use the new position-based read-write flags
+ instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
+ pinfo2 field.
+ * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+ New macros.
+ (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
+ (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
+ (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
+ (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
+ (micromips_opcodes): Use the new position-based read-write flags
+ instead of field-based ones.
+ * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
+ (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
+ of field-based flags.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
+ (WR_SP): Replace with...
+ (MOD_SP): ...this.
+ (mips16_opcodes): Update accordingly.
+ * mips-dis.c (print_insn_mips16): Likewise.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (mips16_opcodes): Reformat.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
+ for operands that are hard-coded to $0.
+ * micromips-opc.c (micromips_opcodes): Likewise.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
+ for the single-operand forms of JALR and JALR.HB.
+ * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
+ and JALRS.HB.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
+ instructions. Fix them to use WR_MACC instead of WR_CC and
+ add missing RD_MACCs.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
+
+2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
+
+2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
+ Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Sergey Lega <sergey.s.lega@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * i386-dis-evex.h: New.
+ * i386-dis.c (OP_Rounding): New.
+ (VPCMP_Fixup): New.
+ (OP_Mask): New.
+ (Rdq): New.
+ (XMxmmq): New.
+ (EXdScalarS): New.
+ (EXymm): New.
+ (EXEvexHalfBcstXmmq): New.
+ (EXxmm_mdq): New.
+ (EXEvexXGscat): New.
+ (EXEvexXNoBcst): New.
+ (VPCMP): New.
+ (EXxEVexR): New.
+ (EXxEVexS): New.
+ (XMask): New.
+ (MaskG): New.
+ (MaskE): New.
+ (MaskR): New.
+ (MaskVex): New.
+ (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
+ evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
+ evex_rounding_mode, evex_sae_mode, mask_mode.
+ (USE_EVEX_TABLE): New.
+ (EVEX_TABLE): New.
+ (EVEX enum): New.
+ (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
+ REG_EVEX_0F38C7.
+ (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
+ MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
+ MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
+ MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
+ MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
+ MOD_EVEX_0F38C7_REG_6.
+ (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
+ PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
+ PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
+ PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
+ PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
+ PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
+ PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
+ PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
+ PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
+ PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
+ PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
+ PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
+ PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
+ PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
+ PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
+ PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
+ PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
+ PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
+ PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
+ PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
+ PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
+ PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
+ PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
+ PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
+ PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
+ PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
+ PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
+ PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
+ PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
+ PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
+ PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
+ PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
+ PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
+ PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
+ PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
+ PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
+ PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
+ PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
+ PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
+ PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
+ PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
+ PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
+ PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
+ PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
+ PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
+ PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
+ PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
+ PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
+ PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
+ PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
+ PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
+ PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
+ PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
+ PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
+ PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
+ PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
+ PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
+ PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
+ PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
+ PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
+ PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
+ PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
+ PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
+ PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
+ PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
+ PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
+ PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
+ PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
+ PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
+ PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
+ PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
+ PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
+ PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
+ PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
+ PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
+ PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
+ PREFIX_EVEX_0F3A55.
+ (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
+ VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
+ VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
+ VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
+ VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
+ VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
+ VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
+ VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
+ VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
+ VEX_W_0F3A32_P_2_LEN_0.
+ (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
+ EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
+ EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
+ EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
+ EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
+ EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
+ EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
+ EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
+ EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
+ EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
+ EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
+ EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
+ EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
+ EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
+ EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
+ EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
+ EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
+ EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
+ EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
+ EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
+ EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
+ EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
+ EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
+ EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
+ EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
+ EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
+ EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
+ EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
+ EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
+ EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
+ EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
+ EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
+ EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
+ EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
+ EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
+ EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
+ EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
+ EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
+ EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
+ EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
+ EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
+ EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
+ EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
+ EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
+ EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
+ EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
+ EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
+ EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
+ EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
+ EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
+ EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
+ EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
+ EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
+ EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
+ (struct vex): Add fields evex, r, v, mask_register_specifier,
+ zeroing, ll, b.
+ (intel_names_xmm): Add upper 16 registers.
+ (att_names_xmm): Ditto.
+ (intel_names_ymm): Ditto.
+ (att_names_ymm): Ditto.
+ (names_zmm): New.
+ (intel_names_zmm): Ditto.
+ (att_names_zmm): Ditto.
+ (names_mask): Ditto.
+ (intel_names_mask): Ditto.
+ (att_names_mask): Ditto.
+ (names_rounding): Ditto.
+ (names_broadcast): Ditto.
+ (x86_64_table): Add escape to evex-table.
+ (reg_table): Include reg_table evex-entries from
+ i386-dis-evex.h. Fix prefetchwt1 instruction.
+ (prefix_table): Add entries for new instructions.
+ (vex_table): Ditto.
+ (vex_len_table): Ditto.
+ (vex_w_table): Ditto.
+ (mod_table): Ditto.
+ (get_valid_dis386): Properly handle new instructions.
+ (print_insn): Handle zmm and mask registers, print mask operand.
+ (intel_operand_size): Support EVEX, new modes and sizes.
+ (OP_E_register): Handle new modes.
+ (OP_E_memory): Ditto.
+ (OP_G): Ditto.
+ (OP_XMM): Ditto.
+ (OP_EX): Ditto.
+ (OP_VEX): Ditto.
+ * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
+ CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
+ CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
+ (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
+ CpuAVX512PF and CpuVREX.
+ (operand_type_init): Add OPERAND_TYPE_REGZMM,
+ OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
+ (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
+ StaticRounding, SAE, Disp8MemShift, NoDefMask.
+ (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
+ * i386-init.h: Regenerate.
+ * i386-opc.h (CpuAVX512F): New.
+ (CpuAVX512CD): New.
+ (CpuAVX512ER): New.
+ (CpuAVX512PF): New.
+ (CpuVREX): New.
+ (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
+ cpuavx512pf and cpuvrex fields.
+ (VecSIB): Add VecSIB512.
+ (EVex): New.
+ (Masking): New.
+ (VecESize): New.
+ (Broadcast): New.
+ (StaticRounding): New.
+ (SAE): New.
+ (Disp8MemShift): New.
+ (NoDefMask): New.
+ (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
+ staticrounding, sae, disp8memshift and nodefmask.
+ (RegZMM): New.
+ (Zmmword): Ditto.
+ (Vec_Disp8): Ditto.
+ (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
+ fields.
+ (RegVRex): New.
+ * i386-opc.tbl: Add AVX512 instructions.
+ * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
+ registers, mask registers.
+ * i386-tbl.h: Regenerate.
-2012-11-21 David Holsgrove <david.holsgrove@xilinx.com>
+2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
+
+ PR gas/15220
+ * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
+ Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
+
+2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
+ PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
+ PREFIX_0F3ACC.
+ (prefix_table): Updated.
+ (three_byte_table): Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
+ (cpu_flags): Add CpuSHA.
+ (i386_cpu_flags): Add cpusha.
+ * i386-init.h: Regenerate.
+ * i386-opc.h (CpuSHA): New.
+ (CpuUnused): Restored.
+ (i386_cpu_flags): Add cpusha.
+ * i386-opc.tbl: Add SHA instructions.
+ * i386-tbl.h: Regenerate.
- * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
- * microblaze-opcm.h (microblaze_instr): Likewise
+2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * i386-dis.c (BND_Fixup): New.
+ (Ebnd): New.
+ (Ev_bnd): New.
+ (Gbnd): New.
+ (BND): New.
+ (v_bnd_mode): New.
+ (bnd_mode): New.
+ (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
+ MOD_0F1B_PREFIX_1.
+ (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
+ (dis tables): Replace XX with BND for near branch and call
+ instructions.
+ (prefix_table): Add new entries.
+ (mod_table): Likewise.
+ (names_bnd): New.
+ (intel_names_bnd): New.
+ (att_names_bnd): New.
+ (BND_PREFIX): New.
+ (prefix_name): Handle BND_PREFIX.
+ (print_insn): Initialize names_bnd.
+ (intel_operand_size): Handle new modes.
+ (OP_E_register): Likewise.
+ (OP_E_memory): Likewise.
+ (OP_G): Likewise.
+ * i386-gen.c (cpu_flag_init): Add CpuMPX.
+ (cpu_flags): Add CpuMPX.
+ (operand_type_init): Add RegBND.
+ (opcode_modifiers): Add BNDPrefixOk.
+ (operand_types): Add RegBND.
+ * i386-init.h: Regenerate.
+ * i386-opc.h (CpuMPX): New.
+ (CpuUnused): Comment out.
+ (i386_cpu_flags): Add cpumpx.
+ (BNDPrefixOk): New.
+ (i386_opcode_modifier): Add bndprefixok.
+ (RegBND): New.
+ (i386_operand_type): Add regbnd.
+ * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
+ Add MPX instructions and bnd prefix.
+ * i386-reg.tbl: Add bnd0-bnd3 registers.
+ * i386-tbl.h: Regenerate.
-2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
- * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
- * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
+ * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
+ ATTRIBUTE_UNUSED.
-2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
- H.J. Lu <hongjiu.lu@intel.com>
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
- PR gas/14859
- * i386-opc.tbl: Fix opcode for 64-bit jecxz.
+ * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
+ special rules.
+ * Makefile.in: Regenerate.
+ * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
+ all fields. Reformat.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c: Include mips-formats.h.
+ (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
+ static arrays.
+ (decode_mips16_operand): New function.
+ * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
+ (print_insn_arg): Handle OP_ENTRY_EXIT list.
+ Abort for OP_SAVE_RESTORE_LIST.
+ (print_mips16_insn_arg): Change interface. Use mips_operand
+ structures. Delete GET_OP_S. Move GET_OP definition to...
+ (print_insn_mips16): ...here. Call init_print_arg_state.
+ Update the call to print_mips16_insn_arg.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-formats.h: New file.
+ * mips-opc.c: Include mips-formats.h.
+ (reg_0_map): New static array.
+ (decode_mips_operand): New function.
+ * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
+ (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
+ (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
+ (int_c_map): New static arrays.
+ (decode_micromips_operand): New function.
+ * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
+ (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
+ (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
+ (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
+ (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
+ (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
+ (micromips_imm_b_map, micromips_imm_c_map): Delete.
+ (print_reg): New function.
+ (mips_print_arg_state): New structure.
+ (init_print_arg_state, print_insn_arg): New functions.
+ (print_insn_args): Change interface and use mips_operand structures.
+ Delete GET_OP_S. Move GET_OP definition to...
+ (print_insn_mips): ...here. Update the call to print_insn_args.
+ (print_insn_micromips): Use print_insn_args.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
+ in macros.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
+ ADDA.S, MULA.S and SUBA.S.
+
+2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/13572
+ * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
* i386-tbl.h: Regenerated.
-2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.txt: Fix srstu and strag opcodes.
-
-2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
-
- * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
- update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
- and increase MAX_OPCODES.
- (op_code_struct): add mbar and sleep
- * microblaze-opcm.h (microblaze_instr): add mbar
- Define IMM_MBAR and IMM5_MBAR_MASK
- * microblaze-dis.c: Add get_field_imm5_mbar
- (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
-
-2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
-
- * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
- * microblaze-opcm.h (microblaze_instr): add clz
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
-2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
+ and SD A(B) macros up.
+ * micromips-opc.c (micromips_opcodes): Likewise.
- * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
- lhur, lwr, sbr, shr, swr
- * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
- swr
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
-2012-11-09 Nick Clifton <nickc@redhat.com>
+ * mips16-opc.c: Add entries for argumentless "entry" and "exit"
+ instructions.
- * configure.in: Add bfd_v850_rh850_arch.
- * configure: Regenerate.
- * disassemble.c (disassembler): Likewise.
-
-2012-11-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
- * ia64-gen.c (fetch_insn_class): Likewise.
-
-2012-11-08 Alan Modra <amodra@gmail.com>
-
- * po/POTFILES.in: Regenerate.
-
-2012-11-05 Alan Modra <amodra@gmail.com>
-
- * configure.in: Apply 2012-09-10 change to config.in here.
-
-2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
- * s390-mkopc.c: Accept empty lines in s390-opc.txt.
- * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
- and RRF_RMRR.
- * s390-opc.txt: Add new instructions. New instruction type for lptea.
+ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
+ MDMX-like instructions.
+ * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
+ printing "Q" operands for INSN_5400 instructions.
-2012-10-26 Christian Groessler <chris@groessler.org>
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
- * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
- trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
- non-existing opcode trtrb.
- * z8k-opc.h: Regenerate.
+ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
+ "+S" for "cins".
+ * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
+ Combine cases.
-2012-10-26 Alan Modra <amodra@gmail.com>
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
- * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
+ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
+ "jalx".
+ * mips16-opc.c (mips16_opcodes): Likewise.
+ * micromips-opc.c (micromips_opcodes): Likewise.
+ * mips-dis.c (print_insn_args, print_mips16_insn_arg)
+ (print_insn_mips16): Handle "+i".
+ (print_insn_micromips): Likewise. Conditionally preserve the
+ ISA bit for "a" but not for "+i".
-2012-10-24 Roland McGrath <mcgrathr@google.com>
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
- * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
- set rex_used to rex.
+ * micromips-opc.c (WR_mhi): Rename to..
+ (WR_mh): ...this.
+ (micromips_opcodes): Update "movep" entry accordingly. Replace
+ "mh,mi" with "mh".
+ * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
+ (micromips_to_32_reg_h_map1): ...this.
+ (micromips_to_32_reg_i_map): Rename to...
+ (micromips_to_32_reg_h_map2): ...this.
+ (print_micromips_insn): Remove "mi" case. Print both registers
+ in the pair for "mh".
-2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
- * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
+ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
+ * micromips-opc.c (micromips_opcodes): Likewise.
+ * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
+ and "+T" handling. Check for a "0" suffix when deciding whether to
+ use coprocessor 0 names. In that case, also check for ",H" selectors.
-2012-10-18 Tom Tromey <tromey@redhat.com>
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
- * tic54x-dis.c (print_instruction): Don't use K&R style.
- (print_parallel_instruction, sprint_dual_address)
- (sprint_indirect_address, sprint_direct_address, sprint_mmr)
- (sprint_cc2, sprint_condition): Likewise.
+ * s390-opc.c (J12_12, J24_24): New macros.
+ (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
+ (MASK_MII_UPI): Rename to MASK_MII_UPP.
+ * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
-2012-10-18 Kai Tietz <ktietz@redhat.com>
+2013-07-04 Alan Modra <amodra@gmail.com>
- * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
- value with a default.
- (do_special_encoding): Likewise.
- (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
- variables with default.
- * arc-dis.c (write_comments_): Don't use strncat due
- size of state->commentBuffer pointer isn't predictable.
+ * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
-2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
- rmr_el3; remove daifset and daifclr.
-
-2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-opc.c (operand_general_constraint_met_p): Change to check
- the alignment of addr.offset.imm instead of that of shifter.amount for
- operand type AARCH64_OPND_ADDR_UIMM12.
-
-2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * arm-dis.c: Use preferred form of vrint instruction variants
- for disassembly.
-
-2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
-
- * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
- * i386-init.h: Regenerated.
+2013-06-26 Nick Clifton <nickc@redhat.com>
-2012-10-05 Peter Bergner <bergner@vnet.ibm.com>
+ * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
+ field when checking for type 2 nop.
+ * rx-decode.c: Regenerate.
- * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
- * ppc-opc.c (VBA): New define.
- (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
- mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
+2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
-2012-10-04 Nick Clifton <nickc@redhat.com>
+ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
+ and "movep" macros.
- * v850-dis.c (disassemble): Place square parentheses around second
- register operand of clr1, not1, set1 and tst1 instructions.
+2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
-2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+ * mips-dis.c (is_mips16_plt_tail): New function.
+ (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
+ word.
+ (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
- * s390-mkopc.c: Support new option zEC12.
- * s390-opc.c: Add new instruction formats.
- * s390-opc.txt: Add new instructions for zEC12.
+2013-06-21 DJ Delorie <dj@redhat.com>
-2012-09-27 Anthony Green <green@moxielogic.com>
+ * msp430-decode.opc: New.
+ * msp430-decode.c: New/generated.
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
+ (MAINTAINER_CLEANFILES): Likewise.
+ Add rule to build msp430-decode.c frommsp430decode.opc
+ using the opc2c program.
+ * Makefile.in: Regenerate.
+ * configure.in: Add msp430-decode.lo to msp430 architecture files.
+ * configure: Regenerate.
- * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
- * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
+2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
-2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+ * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
+ (SYMTAB_AVAILABLE): Removed.
+ (#include "elf/aarch64.h): Ditto.
- * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
- CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
- and CPU_BTVER2_FLAGS.
- * i386-init.h: Regenerated.
+2013-06-17 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * micromips-opc.c (EVA): Define.
+ (TLBINV): Define.
+ (micromips_opcodes): Add EVA opcodes.
+ * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
+ (print_insn_args): Handle EVA offsets.
+ (print_insn_micromips): Likewise.
+ * mips-opc.c (EVA): Define.
+ (TLBINV): Define.
+ (mips_builtin_opcodes): Add EVA opcodes.
+
+2013-06-17 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am (mips-opc.lo): Add rules to create automatic
+ dependency files. Pass archdefs.
+ (micromips-opc.lo, mips16-opc.lo): Likewise.
+ * Makefile.in: Regenerate.
-2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+2013-06-14 DJ Delorie <dj@redhat.com>
- * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
- CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
- CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
- CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
- (cpu_flags): Add CpuCX16.
- * i386-opc.h (CpuCX16): New.
- (i386_cpu_flags): Add cpucx16.
- * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
- * i386-tbl.h: Regenerate.
- * i386-init.h: Likewise.
+ * rx-decode.opc (rx_decode_opcode): Bit operations on
+ registers are 32-bit operations, not 8-bit operations.
+ * rx-decode.c: Regenerate.
-2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
- * arm-dis.c: Changed ldra and strl-form mnemonics
- to lda and stl-form.
+ * micromips-opc.c (IVIRT): New define.
+ (IVIRT64): New define.
+ (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+ tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
-2012-09-18 Chao-ying Fu <fu@mips.com>
+ * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
+ dmtgc0 to print cp0 names.
- * micromips-opc.c (micromips_opcodes): Correct the encoding of
- the "swxc1" instruction.
+2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
-2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
+ * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
+ argument.
- * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
- the parameter 'inst'.
- (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
- (convert_mov_to_movewide): Change to assert (0) when
- aarch64_wide_constant_p returns FALSE.
+2013-06-08 Catherine Moore <clm@codesourcery.com>
+ Richard Sandiford <rdsandiford@googlemail.com>
-2012-09-14 David Edelsohn <dje.gcc@gmail.com>
+ * micromips-opc.c (D32, D33, MC): Update definitions.
+ (micromips_opcodes): Initialize ase field.
+ * mips-dis.c (mips_arch_choice): Add ase field.
+ (mips_arch_choices): Initialize ase field.
+ (set_default_mips_dis_options): Declare and setup mips_ase.
+ * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
+ MT32, MC): Update definitions.
+ (mips_builtin_opcodes): Initialize ase field.
- * configure: Regenerate.
+2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
-2012-09-14 Anthony Green <green@moxielogic.com>
+ * s390-opc.txt (flogr): Require a register pair destination.
- * moxie-dis.c (print_insn_moxie): Branch targets are relative to
- the address after the branch instruction.
+2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-2012-09-13 Anthony Green <green@moxielogic.com>
+ * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
+ instruction format.
- * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
+2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
-2012-09-10 Matthias Klose <doko@ubuntu.com>
+ * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
- * config.in: Disable sanity check for kfreebsd.
+2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
-2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
+ * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
+ * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
+ XLS_MASK, PPCVSX2): New defines.
+ (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
+ fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
+ mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
+ mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
+ mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
+ vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
+ vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
+ vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
+ vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
+ vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
+ vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
+ vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
+ vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
+ vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
+ xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
+ xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
+ xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
+ xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
+ <lxvx, stxvx>: New extended mnemonics.
- * configure: Regenerated.
+2013-05-17 Alan Modra <amodra@gmail.com>
-2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
-
- * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
- * ia64-gen.c: Promote completer index type to longlong.
- (irf_operand): Add new register recognition.
- (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
- (lookup_specifier): Add new resource recognition.
- (insert_bit_table_ent): Relax abort condition according to the
- changed completer index type.
- (print_dis_table): Fix printf format for completer index.
- * ia64-ic.tbl: Add a new instruction class.
- * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
- * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
- * ia64-opc.h: Define short names for new operand types.
- * ia64-raw.tbl: Add new RAW resource for DAHR register.
- * ia64-waw.tbl: Add new WAW resource for DAHR register.
+ * ia64-raw.tbl: Replace non-ASCII char.
+ * ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerate.
-2012-08-29 Peter Bergner <bergner@vnet.ibm.com>
+2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
- * ppc-opc.c (VXASHB_MASK): New define.
- (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
+ * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
+ * i386-init.h: Regenerated.
-2012-08-28 Peter Bergner <bergner@vnet.ibm.com>
+2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
- * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
- VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
- (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
- vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
- vupklsh>: Use VXVA_MASK.
- <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
- <mfvscr>: Use VXVAVB_MASK.
- <mtvscr>: Use VXVDVA_MASK.
- <vspltb>: Use VXUIMM4_MASK.
- <vsplth>: Use VXUIMM3_MASK.
- <vspltw>: Use VXUIMM2_MASK.
+ * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
+ * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
+ check from [0, 255] to [-128, 255].
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-05-09 Andrew Pinski <apinski@cavium.com>
- * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
+ * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
+ Add INSN_VIRT and INSN_VIRT64 to mips64r2.
+ (parse_mips_dis_option): Handle the virt option.
+ (print_insn_args): Handle "+J".
+ (print_mips_disassembler_options): Print out message about virt64.
+ * mips-opc.c (IVIRT): New define.
+ (IVIRT64): New define.
+ (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+ tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
+ Move rfe to the bottom as it conflicts with tlbgp.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-05-09 Alan Modra <amodra@gmail.com>
- * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
+ * ppc-opc.c (extract_vlesi): Properly sign extend.
+ (extract_vlensi): Likewise. Comment reason for setting invalid.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-05-02 Nick Clifton <nickc@redhat.com>
- * arm-dis.c (neon_opcodes): Handle VMULL.P64.
+ * msp430-dis.c: Add support for MSP430X instructions.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
- * arm-dis.c (neon_opcodes): Add support for AES instructions.
+ * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
+ to "eccinj".
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-17 Wei-chen Wang <cole945@gmail.com>
- * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
- conversions.
+ PR binutils/15369
+ * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
+ of CGEN_CPU_ENDIAN.
+ (hash_insns_list): Likewise.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
- * arm-dis.c (coprocessor_opcodes): Add VRINT.
- (neon_opcodes): Likewise.
+ * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
+ warning workaround.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-08 Jan Beulich <jbeulich@suse.com>
- * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
- variants.
- (neon_opcodes): Likewise.
+ * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
+ * i386-tbl.h: Re-generate.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-06 David S. Miller <davem@davemloft.net>
- * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
- (neon_opcodes): Likewise.
+ * sparc-dis.c (compare_opcodes): When encountering multiple aliases
+ of an opcode, prefer the one with F_PREFERRED set.
+ * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
+ lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
+ ops. Make 64-bit VIS logical ops have "d" suffix in their names,
+ mark existing mnenomics as aliases. Add "cc" suffix to edge
+ instructions generating condition codes, mark existing mnenomics
+ as aliases. Add "fp" prefix to VIS compare instructions, mark
+ existing mnenomics as aliases.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+2013-04-03 Nick Clifton <nickc@redhat.com>
- * arm-dis.c (coprocessor_opcodes): Add VSEL.
- (print_insn_coprocessor): Add new %<>c bitfield format
- specifier.
+ * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
+ destination address by subtracting the operand from the current
+ address.
+ * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
+ a positive value in the insn.
+ (extract_u16_loop): Do not negate the returned value.
+ (D16_LOOP): Add V850_INVERSE_PCREL flag.
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ (ceilf.sw): Remove duplicate entry.
+ (cvtf.hs): New entry.
+ (cvtf.sh): Likewise.
+ (fmaf.s): Likewise.
+ (fmsf.s): Likewise.
+ (fnmaf.s): Likewise.
+ (fnmsf.s): Likewise.
+ (maddf.s): Restrict to E3V5 architectures.
+ (msubf.s): Likewise.
+ (nmaddf.s): Likewise.
+ (nmsubf.s): Likewise.
- * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
- (thumb32_opcodes): Likewise.
- (print_arm_insn): Add support for %<>T formatter.
+2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * i386-dis.c (get_sib): Add the sizeflag argument. Properly
+ check address mode.
+ (print_insn): Pass sizeflag to get_sib.
- * arm-dis.c (arm_opcodes): Add HLT.
- (thumb_opcodes): Likewise.
+2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ PR binutils/15068
+ * tic6x-dis.c: Add support for displaying 16-bit insns.
- * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
+2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ PR gas/15095
+ * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
+ individual msb and lsb halves in src1 & src2 fields. Discard the
+ src1 (lsb) value and only use src2 (msb), discarding bit 0, to
+ follow what Ti SDK does in that case as any value in the src1
+ field yields the same output with SDK disassembler.
- * arm-dis.c (arm_opcodes): Add SEVL.
- (thumb_opcodes): Likewise.
- (thumb32_opcodes): Likewise.
+2013-03-12 Michael Eager <eager@eagercon.com>
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
- * arm-dis.c (data_barrier_option): New function.
- (print_insn_arm): Use data_barrier_option.
- (print_insn_thumb32): Use data_barrier_option.
+2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
+ * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
- * arm-dis.c (COND_UNCOND): New constant.
- (print_insn_coprocessor): Add support for %u format specifier.
- (print_insn_neon): Likewise.
+2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-2012-08-21 David S. Miller <davem@davemloft.net>
+ * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
- * sparc-opc.c (4-argument crypto instructions): Fix encoding using
- F3F4 macro.
+2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-2012-08-20 Edmar Wienskoski <edmar@freescale.com>
+ * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
- * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
- vabsduh, vabsduw, mviwsplt.
+2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
+ * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
+ (thumb32_opcodes): Likewise.
+ (print_insn_thumb32): Handle 'S' control char.
- * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
- CPU_BTVER2_FLAGS.
+2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
- * i386-opc.h: Update CpuPRFCHW comment.
+ * lm32-desc.c: Regenerate.
- * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2012-08-17 Nick Clifton <nickc@redhat.com>
+2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
- * po/uk.po: New Ukranian translation.
- * configure.in (ALL_LINGUAS): Add uk.
- * configure: Regenerate.
+ * i386-reg.tbl (riz): Add RegRex64.
+ * i386-tbl.h: Regenerated.
-2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
+2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
- * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
- RBX for the third operand.
- <"lswi">: Use RAX for second and NBI for the third operand.
+ * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
+ (aarch64_feature_crc): New static.
+ (CRC): New macro.
+ (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
+ crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
+ * aarch64-asm-2.c: Re-generate.
+ * aarch64-dis-2.c: Ditto.
+ * aarch64-opc-2.c: Ditto.
-2012-08-15 DJ Delorie <dj@redhat.com>
+2013-02-27 Alan Modra <amodra@gmail.com>
- * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
- operands, so that data addresses can be corrected when not
- ES-overridden.
+ * rl78-decode.opc (rl78_decode_opcode): Fix typo.
* rl78-decode.c: Regenerate.
- * rl78-dis.c (print_insn_rl78): Make order of modifiers
- irrelevent. When the 'e' specifier is used on an operand and no
- ES prefix is provided, adjust address to make it absolute.
-2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
+2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
- * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
-
-2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
+ * rl78-decode.opc: Fix encoding of DIVWU insn.
+ * rl78-decode.c: Regenerate.
- * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
+2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
-2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
+ PR gas/15159
+ * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
- * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
- macros, use local variables for info struct member accesses,
- update the type of the variable used to hold the instruction
- word.
- (print_insn_mips, print_mips16_insn_arg): Likewise.
- (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
- local variables for info struct member accesses.
- (print_insn_micromips): Add GET_OP_S local macro.
- (_print_insn_mips): Update the type of the variable used to hold
- the instruction word.
-
-2012-08-13 Ian Bolton <ian.bolton@arm.com>
- Laurent Desnogues <laurent.desnogues@arm.com>
- Jim MacArthur <jim.macarthur@arm.com>
- Marcus Shawcroft <marcus.shawcroft@arm.com>
- Nigel Stephens <nigel.stephens@arm.com>
- Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
- Richard Earnshaw <rearnsha@arm.com>
- Sofiane Naci <sofiane.naci@arm.com>
- Tejas Belagod <tejas.belagod@arm.com>
- Yufeng Zhang <yufeng.zhang@arm.com>
-
- * Makefile.am: Add AArch64.
- * Makefile.in: Regenerate.
- * aarch64-asm.c: New file.
- * aarch64-asm.h: New file.
- * aarch64-dis.c: New file.
- * aarch64-dis.h: New file.
- * aarch64-gen.c: New file.
- * aarch64-opc.c: New file.
- * aarch64-opc.h: New file.
- * aarch64-tbl.h: New file.
- * configure.in: Add AArch64.
- * configure: Regenerate.
- * disassemble.c: Add AArch64.
- * aarch64-asm-2.c: New file (automatically generated).
- * aarch64-dis-2.c: New file (automatically generated).
- * aarch64-opc-2.c: New file (automatically generated).
- * po/POTFILES.in: Regenerate.
+ * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
+ (cpu_flags): Add CpuSMAP.
-2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c (micromips_opcodes): Update comment.
- * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
- instructions for IOCT as appropriate.
- * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
- opcode_is_member.
- * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
- the result of a check for the -Wno-missing-field-initializers
- GCC option.
- * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
- (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
- compilation.
- (mips16-opc.lo): Likewise.
- (micromips-opc.lo): Likewise.
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
- * Makefile.in: Regenerate.
+ * i386-opc.h (CpuSMAP): New.
+ (i386_cpu_flags): Add cpusmap.
-2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+ * i386-opc.tbl: Add clac and stac.
- PR gas/14423
- * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
* i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
-2012-08-09 Nick Clifton <nickc@redhat.com>
+2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
- * po/vi.po: Updated Vietnamese translation.
+ * metag-dis.c: Initialize outf->bytes_per_chunk to 4
+ which also makes the disassembler output be in little
+ endian like it should be.
-2012-08-07 Roland McGrath <mcgrathr@google.com>
+2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
- * i386-dis.c (reg_table): Fill out REG_0F0D table with
- AMD-reserved cases as "prefetch".
- (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
- (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
- (reg_table): Use those under REG_0F18.
- (mod_table): Add those cases as "nop/reserved".
+ * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
+ fields to NULL.
+ (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
-2012-08-07 Jan Beulich <jbeulich@suse.com>
+2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
- * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
+ * mips-dis.c (is_compressed_mode_p): Only match symbols from the
+ section disassembled.
-2012-08-06 Roland McGrath <mcgrathr@google.com>
+2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * i386-dis.c (print_insn): Print spaces between multiple excess
- prefixes. Return actual number of excess prefixes consumed,
- not always one.
+ * arm-dis.c: Update strht pattern.
- * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
+2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
-2012-08-06 Roland McGrath <mcgrathr@google.com>
- Victor Khimenko <khim@google.com>
- H.J. Lu <hongjiu.lu@intel.com>
+ * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
+ single-float. Disable ll, lld, sc and scd for EE. Disable the
+ trunc.w.s macro for EE.
- * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
- (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
- (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
- (OP_E_register): Likewise.
- (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
+2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
+ Andrew Jenner <andrew@codesourcery.com>
-2012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+ Based on patches from Altera Corporation.
- * configure.in: Formatting.
- * configure: Regenerate.
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
+ nios2-opc.c.
+ * Makefile.in: Regenerated.
+ * configure.in: Add case for bfd_nios2_arch.
+ * configure: Regenerated.
+ * disassemble.c (ARCH_nios2): Define.
+ (disassembler): Add case for bfd_arch_nios2.
+ * nios2-dis.c: New file.
+ * nios2-opc.c: New file.
-201
2-08-01 Alan Modra <amodra@gmail.com>
+201
3-02-04 Alan Modra <amodra@gmail.com>
- * h8300-dis.c: Fix printf arg warnings.
- * i960-dis.c: Likewise.
- * mips-dis.c: Likewise.
- * pdp11-dis.c: Likewise.
- * sh-dis.c: Likewise.
- * v850-dis.c: Likewise.
- * configure.in: Formatting.
- * configure: Regenerate.
- * rl78-decode.c: Regenerate.
* po/POTFILES.in: Regenerate.
-
-2012-07-31 Chao-Ying Fu <fu@mips.com>
- Catherine Moore <clm@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
- (DSP_VOLA): Likewise.
- (D32, D33): Likewise.
- (micromips_opcodes): Add DSP ASE instructions.
- * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
- <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
-
-2012-07-31 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
- instruction group. Mark as requiring AVX2.
- * i386-tbl.h: Re-generate.
-
-2012-07-30 Nick Clifton <nickc@redhat.com>
-
- * po/opcodes.pot: Updated template.
- * po/es.po: Updated Spanish translation.
- * po/fi.po: Updated Finnish translation.
-
-2012-07-27 Mike Frysinger <vapier@gentoo.org>
-
- * configure.in (BFD_VERSION): Run bfd/configure --version and
- parse the output of that.
- * configure: Regenerate.
-
-2012-07-25 James Lemke <jwlemke@codesourcery.com>
-
- * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
-
-2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
- Dr David Alan Gilbert <dave@treblig.org>
-
- PR binutils/13135
- * arm-dis.c: Add necessary casts for printing integer values.
- Use %s when printing string values.
- * hppa-dis.c: Likewise.
- * m68k-dis.c: Likewise.
- * microblaze-dis.c: Likewise.
- * mips-dis.c: Likewise.
- * sparc-dis.c: Likewise.
-
-2012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- PR binutils/14355
- * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
- (VEX_LEN_0FXOP_08_CD): Likewise.
- (VEX_LEN_0FXOP_08_CE): Likewise.
- (VEX_LEN_0FXOP_08_CF): Likewise.
- (VEX_LEN_0FXOP_08_EC): Likewise.
- (VEX_LEN_0FXOP_08_ED): Likewise.
- (VEX_LEN_0FXOP_08_EE): Likewise.
- (VEX_LEN_0FXOP_08_EF): Likewise.
- (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
- vpcomub, vpcomuw, vpcomud, vpcomuq.
- (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
- VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
- VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
- VEX_LEN_0FXOP_08_EF.
-
-2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
-
- * i386-dis.c (PREFIX_0F38F6): New.
- (prefix_table): Add adcx, adox instructions.
- (three_byte_table): Use PREFIX_0F38F6.
- (mod_table): Add rdseed instruction.
- * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
- (cpu_flags): Likewise.
- * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
- (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
- * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
- prefetchw.
- * i386-tbl.h: Regenerate.
- * i386-init.h: Likewise.
-
-2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
-
- * mips-dis.c: Remove gratuitous newline.
-
-2012-07-05 Sean Keys <skeys@ipdatasys.com>
-
- * xgate-dis.c: Removed an IF statement that will
- always be false due to overlapping operand masks.
- * xgate-opc.c: Corrected 'com' opcode entry and
- fixed spacing.
-
-2012-07-02 Roland McGrath <mcgrathr@google.com>
-
- * i386-opc.tbl: Add RepPrefixOk to nop.
- * i386-tbl.h: Regenerate.
-
-2012-06-28 Nick Clifton <nickc@redhat.com>
-
- * po/vi.po: Updated Vietnamese translation.
-
-2012-06-22 Roland McGrath <mcgrathr@google.com>
-
- * i386-opc.tbl: Add RepPrefixOk to ret.
- * i386-tbl.h: Regenerate.
-
- * i386-opc.h (RepPrefixOk): New enum constant.
- (i386_opcode_modifier): New bitfield 'repprefixok'.
- * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
- * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
- instructions that have IsString.
- * i386-tbl.h: Regenerate.
-
-2012-06-11 Andreas Schwab <schwab@linux-m68k.org>
-
- * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
- (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
- (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
- (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
- (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
- (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
- (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
- (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
- (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
-
-2012-05-19 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
- (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
-
-2012-05-18 Alan Modra <amodra@gmail.com>
-
- * ia64-opc.c: Remove #include "ansidecl.h".
- * z8kgen.c: Include sysdep.h first.
-
- * arc-dis.c: Include sysdep.h first, remove some redundant includes.
- * bfin-dis.c: Likewise.
- * i860-dis.c: Likewise.
- * ia64-dis.c: Likewise.
- * ia64-gen.c: Likewise.
- * m68hc11-dis.c: Likewise.
- * mmix-dis.c: Likewise.
- * msp430-dis.c: Likewise.
- * or32-dis.c: Likewise.
- * rl78-dis.c: Likewise.
- * rx-dis.c: Likewise.
- * tic4x-dis.c: Likewise.
- * tilegx-opc.c: Likewise.
- * tilepro-opc.c: Likewise.
- * rx-decode.c: Regenerate.
-
-2012-05-17 James Lemke <jwlemke@codesourcery.com>
-
- * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
-
-2012-05-17 James Lemke <jwlemke@codesourcery.com>
-
- * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
-
-2012-05-17 Daniel Richard G. <skunk@iskunk.org>
- Nick Clifton <nickc@redhat.com>
-
- PR 14072
- * configure.in: Add check that sysdep.h has been included before
- any system header files.
- * configure: Regenerate.
- * config.in: Regenerate.
- * sysdep.h: Generate an error if included before config.h.
- * alpha-opc.c: Include sysdep.h before any other header file.
- * alpha-dis.c: Likewise.
- * avr-dis.c: Likewise.
- * cgen-opc.c: Likewise.
- * cr16-dis.c: Likewise.
- * cris-dis.c: Likewise.
- * crx-dis.c: Likewise.
- * d10v-dis.c: Likewise.
- * d10v-opc.c: Likewise.
- * d30v-dis.c: Likewise.
- * d30v-opc.c: Likewise.
- * h8500-dis.c: Likewise.
- * i370-dis.c: Likewise.
- * i370-opc.c: Likewise.
- * m10200-dis.c: Likewise.
- * m10300-dis.c: Likewise.
- * micromips-opc.c: Likewise.
- * mips-opc.c: Likewise.
- * mips61-opc.c: Likewise.
- * moxie-dis.c: Likewise.
- * or32-opc.c: Likewise.
- * pj-dis.c: Likewise.
- * ppc-dis.c: Likewise.
- * ppc-opc.c: Likewise.
- * s390-dis.c: Likewise.
- * sh-dis.c: Likewise.
- * sh64-dis.c: Likewise.
- * sparc-dis.c: Likewise.
- * sparc-opc.c: Likewise.
- * spu-dis.c: Likewise.
- * tic30-dis.c: Likewise.
- * tic54x-dis.c: Likewise.
- * tic80-dis.c: Likewise.
- * tic80-opc.c: Likewise.
- * tilegx-dis.c: Likewise.
- * tilepro-dis.c: Likewise.
- * v850-dis.c: Likewise.
- * v850-opc.c: Likewise.
- * vax-dis.c: Likewise.
- * w65-dis.c: Likewise.
- * xgate-dis.c: Likewise.
- * xtensa-dis.c: Likewise.
- * rl78-decode.opc: Likewise.
* rl78-decode.c: Regenerate.
- * rx-decode.opc: Likewise.
* rx-decode.c: Regenerate.
-2012-05-17 Alan Modra <amodra@gmail.com>
-
- * ppc_dis.c: Don't include elf/ppc.h.
-
-2012-05-16 Meador Inge <meadori@codesourcery.com>
-
- * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
- to PUSH/POP {reg}.
-
-2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
- Stephane Carrez <stcarrez@nerim.fr>
-
- * configure.in: Add S12X and XGATE co-processor support to m68hc11
- target.
- * disassemble.c: Likewise.
- * configure: Regenerate.
- * m68hc11-dis.c: Make objdump output more consistent, use hex
- instead of decimal and use 0x prefix for hex.
- * m68hc11-opc.c: Add S12X and XGATE opcodes.
-
-2012-05-14 James Lemke <jwlemke@codesourcery.com>
-
- * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
- (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
- (vle_opcd_indices): New array.
- (lookup_vle): New function.
- (disassemble_init_powerpc): Revise for second (VLE) opcode table.
- (print_insn_powerpc): Likewise.
- * ppc-opc.c: Likewise.
-
-2012-05-14 Catherine Moore <clm@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
- Rhonda Wittels <rhonda@codesourcery.com>
- Nathan Froyd <froydnj@codesourcery.com>
-
- * ppc-opc.c (insert_arx, extract_arx): New functions.
- (insert_ary, extract_ary): New functions.
- (insert_li20, extract_li20): New functions.
- (insert_rx, extract_rx): New functions.
- (insert_ry, extract_ry): New functions.
- (insert_sci8, extract_sci8): New functions.
- (insert_sci8n, extract_sci8n): New functions.
- (insert_sd4h, extract_sd4h): New functions.
- (insert_sd4w, extract_sd4w): New functions.
- (insert_vlesi, extract_vlesi): New functions.
- (insert_vlensi, extract_vlensi): New functions.
- (insert_vleui, extract_vleui): New functions.
- (insert_vleil, extract_vleil): New functions.
- (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
- (BI16, BI32, BO32, B8): New.
- (B15, B24, CRD32, CRS): New.
- (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
- (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
- (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
- (SH6_MASK): Use PPC_OPSHIFT_INV.
- (SI8, UI5, OIMM5, UI7, BO16): New.
- (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
- (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
- (ALLOW8_SPRG): New.
- (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
- (OPVUP, OPVUP_MASK OPVUP): New
- (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
- (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
- (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
- (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
- (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
- (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
- (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
- (SE_IM5, SE_IM5_MASK): New.
- (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
- (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
- (BO32DNZ, BO32DZ): New.
- (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
- (PPCVLE): New.
- (powerpc_opcodes): Add new VLE instructions. Update existing
- instruction to include PPCVLE if supported.
- * ppc-dis.c (ppc_opts): Add vle entry.
- (get_powerpc_dialect): New function.
- (powerpc_init_dialect): VLE support.
- (print_insn_big_powerpc): Call get_powerpc_dialect.
- (print_insn_little_powerpc): Likewise.
- (operand_value_powerpc): Handle negative shift counts.
- (print_insn_powerpc): Handle 2-byte instruction lengths.
-
-2012-05-11 Daniel Richard G. <skunk@iskunk.org>
-
- PR binutils/14028
- * configure.in: Invoke ACX_HEADER_STRING.
- * configure: Regenerate.
- * config.in: Regenerate.
- * sysdep.h: If STRINGS_WITH_STRING is defined then include both
- string.h and strings.h.
+2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
-2012-05-11 Nick Clifton <nickc@redhat.com>
+ * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
+ ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
+ * aarch64-asm.c (convert_xtl_to_shll): New function.
+ (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+ calling convert_xtl_to_shll.
+ * aarch64-dis.c (convert_shll_to_xtl): New function.
+ (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+ calling convert_shll_to_xtl.
+ * aarch64-gen.c: Update copyright year.
+ * aarch64-asm-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
+ * aarch64-opc-2.c: Re-generate.
- PR binutils/14006
- * arm-dis.c (print_insn): Fix detection of instruction mode in
- files containing multiple executable sections.
+2013-01-24 Nick Clifton <nickc@redhat.com>
-2012-05-03 Sean Keys <skeys@ipdatasys.com>
-
- * Makefile.in, configure: regenerate
- * disassemble.c (disassembler): Recognize ARCH_XGATE.
- * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
- New functions.
- * configure.in: Recognize xgate.
- * xgate-dis.c, xgate-opc.c: New files for support of xgate
- * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
- and opcode generation for xgate.
-
-2012-04-30 DJ Delorie <dj@redhat.com>
-
- * rx-decode.opc (MOV): Do not sign-extend immediates which are
- already the maximum bit size.
- * rx-decode.c: Regenerate.
-
-2012-04-27 David S. Miller <davem@davemloft.net>
-
- * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
- * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
+ * v850-dis.c: Add support for e3v5 architecture.
+ * v850-opc.c: Likewise.
- * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
- * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
+2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
- * sparc-opc.c (CBCOND): New define.
- (CBCOND_XCC): Likewise.
- (cbcond): New helper macro.
- (sparc_opcodes): Add compare-and-branch instructions.
+ * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
+ * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
+ * aarch64-opc.c (operand_general_constraint_met_p): For
+ AARCH64_MOD_LSL, move the range check on the shift amount before the
+ alignment check; change to call set_sft_amount_out_of_range_error
+ instead of set_imm_out_of_range_error.
+ * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
+ (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
+ 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
+ SIMD_IMM_SFT.
- * sparc-dis.c (print_insn_sparc): Handle ')'.
- * sparc-opc.c (sparc_opcodes): Add crypto instructions.
+2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
- * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
- into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
+ * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
-2012-04-12 David S. Miller <davem@davemloft.net>
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
- * sparc-dis.c (X_DISP10): Define.
- (print_insn_sparc): Handle '='.
+2013-01-15 Nick Clifton <nickc@redhat.com>
-2012-04-01 Mike Frysinger <vapier@gentoo.org>
+ * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
+ values.
+ * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
- * bfin-dis.c (fmtconst): Replace decimal handling with a single
- sprintf call and the '*' field width.
+2013-01-14 Will Newton <will.newton@imgtec.com>
-2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
+ * metag-dis.c (REG_WIDTH): Increase to 64.
- * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
+2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
-2012-03-16 Alan Modra <amodra@gmail.com>
+ * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
+ * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
+ XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
+ (SH6): Update.
+ <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
+ "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
+ "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
+ <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
- * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
- (powerpc_opcd_indices): Bump array size.
- (disassemble_init_powerpc): Set powerpc_opcd_indices entries
- corresponding to unused opcodes to following entry.
- (lookup_powerpc): New function, extracted and optimised from..
- (print_insn_powerpc): ..here.
+2013-01-10 Will Newton <will.newton@imgtec.com>
-2012-03-15 Alan Modra <amodra@gmail.com>
- James Lemke <jwlemke@codesourcery.com>
+ * Makefile.am: Add Meta.
+ * configure.in: Add Meta.
+ * disassemble.c: Add Meta support.
+ * metag-dis.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
- * disassemble.c (disassemble_init_for_target): Handle ppc init.
- * ppc-dis.c (private): New var.
- (powerpc_init_dialect): Don't return calloc failure, instead use
- private.
- (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
- (powerpc_opcd_indices): New array.
- (disassemble_init_powerpc): New function.
- (print_insn_big_powerpc): Don't init dialect here.
- (print_insn_little_powerpc): Likewise.
- (print_insn_powerpc): Start search using powerpc_opcd_indices.
-
-2012-03-10 Edmar Wienskoski <edmar@freescale.com>
-
- * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
- * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
- (PPCVEC2, PPCTMR, E6500): New short names.
- (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
- mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
- lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
- lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
- lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
- optional operands on sync instruction for E6500 target.
-
-2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
-
-2012-02-27 Alan Modra <amodra@gmail.com>
-
- * mt-dis.c: Regenerate.
-
-2012-02-27 Alan Modra <amodra@gmail.com>
-
- * v850-opc.c (extract_v8): Rearrange to make it obvious this
- is the inverse of corresponding insert function.
- (extract_d22, extract_u9, extract_r4): Likewise.
- (extract_d9): Correct sign extension.
- (extract_d16_15): Don't assume "long" is 32 bits, and don't
- rely on implementation defined behaviour for shift right of
- signed types.
- (extract_d16_16, extract_d17_16, extract_i9): Likewise.
- (extract_d23): Likewise, and correct mask.
-
-2012-02-27 Alan Modra <amodra@gmail.com>
-
- * crx-dis.c (print_arg): Mask constant to 32 bits.
- * crx-opc.c (cst4_map): Use int array.
-
-2012-02-27 Alan Modra <amodra@gmail.com>
-
- * arc-dis.c (BITS): Don't use shifts to mask off bits.
- (FIELDD): Sign extend with xor,sub.
-
-2012-02-25 Walter Lee <walt@tilera.com>
-
- * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
- * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
- TILEPRO_OPC_LW_TLS_SN.
-
-2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.h (HLEPrefixNone): New.
- (HLEPrefixLock): Likewise.
- (HLEPrefixAny): Likewise.
- (HLEPrefixRelease): Likewise.
-
-2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (HLE_Fixup1): New.
- (HLE_Fixup2): Likewise.
- (HLE_Fixup3): Likewise.
- (Ebh1): Likewise.
- (Evh1): Likewise.
- (Ebh2): Likewise.
- (Evh2): Likewise.
- (Ebh3): Likewise.
- (Evh3): Likewise.
- (MOD_C6_REG_7): Likewise.
- (MOD_C7_REG_7): Likewise.
- (RM_C6_REG_7): Likewise.
- (RM_C7_REG_7): Likewise.
- (XACQUIRE_PREFIX): Likewise.
- (XRELEASE_PREFIX): Likewise.
- (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
- cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
- Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
- (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
- not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
- MOD_C6_REG_7 and MOD_C7_REG_7.
- (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
- (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
- xtest.
- (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
- (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
-
- * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
- CPU_RTM_FLAGS.
- (cpu_flags): Add CpuHLE and CpuRTM.
- (opcode_modifiers): Add HLEPrefixOk.
-
- * i386-opc.h (CpuHLE): New.
- (CpuRTM): Likewise.
- (HLEPrefixOk): Likewise.
- (i386_cpu_flags): Add cpuhle and cpurtm.
- (i386_opcode_modifier): Add hleprefixok.
-
- * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
- add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
- sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
- operand. Add xacquire, xrelease, xabort, xbegin, xend and
- xtest.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
-2012-01-24 DJ Delorie <dj@redhat.com>
+ * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
+ (match_opcode): Rename to cr16_match_opcode.
- * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
- * rl78-decode.c: Regenerate.
+2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
-2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
+ * mips-dis.c: Add names for CP0 registers of r5900.
+ * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
+ instructions sq and lq.
+ Add support for MIPS r5900 CPU.
+ Add support for 128 bit MMI (Multimedia Instructions).
+ Add support for EE instructions (Emotion Engine).
+ Disable unsupported floating point instructions (64 bit and
+ undefined compare operations).
+ Enable instructions of MIPS ISA IV which are supported by r5900.
+ Disable 64 bit co processor instructions.
+ Disable 64 bit multiplication and division instructions.
+ Disable instructions for co-processor 2 and 3, because these are
+ not supported (preparation for later VU0 support (Vector Unit)).
+ Disable cvt.w.s because this behaves like trunc.w.s and the
+ correct execution can't be ensured on r5900.
+ Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
+ will confuse less developers and compilers.
- PR binutils/10173
- * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
+2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
-2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
+ * aarch64-opc.c (aarch64_print_operand): Change to print
+ AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
+ in comment.
+ * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
+ from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
+ OP_MOV_IMM_WIDE.
- * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
- register and move them after pmove with PSR/PCSR register.
+2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
-2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
+ * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
+ PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
- * i386-dis.c (mod_table): Add vmfunc.
+2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
- * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
- (cpu_flags): CpuVMFUNC.
+ * i386-gen.c (process_copyright): Update copyright year to 2013.
- * i386-opc.h (CpuVMFUNC): New.
- (i386_cpu_flags): Add cpuvmfunc.
+2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
- * i386-opc.tbl: Add vmfunc.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+ * cr16-dis.c (match_opcode,make_instruction): Remove static
+ declaration.
+ (dwordU,wordU): Moved typedefs to opcode/cr16.h
+ (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
-For older changes see ChangeLog-2011
+For older changes see ChangeLog-2012
\f
-Copyright (C) 2012 Free Software Foundation, Inc.
+Copyright (C) 2013 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff