+Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-dis.c (_print_insn_mips): Set target_processor as appropriate.
+ Only recognize instructions for the current target_processor.
+
+start-sanitize-sky
+Tue Jan 27 14:11:04 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c (*): Update to use new arguments in
+ parse/insert/extract/print fns.
+ * txvu-opc.c (*): Likewise.
+
+Mon Jan 26 16:25:51 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c (print_insn): Extract/print fns take pointer to
+ insn now and not insn itself.
+ * txvu-opc.c: insert/extract/print fns take pointer to
+ insn now and not insn itself. Add initial dma,pke,gpuif support.
+ Parse fn no longer needs to set errmsg = NULL for success.
+ (lookup_keyword_{value,name}): New functions.
+ (scan_symbol): New function.
+ (issymchar,SKIP_BLANKS): New macros.
+
+Fri Jan 23 01:49:24 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-opc.c (txvu_operands, UBC): Add extract entry.
+ (txvu_operands, UACCDEST): Not a fake operand.
+ (txvu_operands, UXYZ): Move parse entry to insert entry.
+ (txvu_operands, LVI01): Not a fake operand.
+ (txvu_upper_opcodes): Fix spelling of minii instruction.
+ (printf_vfreg): Print register number with "%02ld".
+ (print_bcftreg): Likewise.
+ (print_accdest): Pass `dest' to _print_dest.
+ (insert_xyz): Renamed from parse_xyz.
+ (parse_dest1,insert_luimm12up6): New functions.
+ (txvu_operands): New operands LUIMM12UP6, LDEST1.
+ (txvu_lower_opcodes): Clean up pass over table.
+ (parse_dotdest1): Fix dest calculation.
+ (_parse_sdest): Fix typo.
+
+end-sanitize-sky
+Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com>
+
+ * d10v-dis.c (PC_MASK): Correct value.
+ (print_operand): If there's a reloc, don't calculate the
+ address because they could be in different sections.
+
+start-sanitize-cygnus
+Thu Jan 22 16:10:32 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.sh: Rewrite to be like simulator's version.
+ * Makefile.am (cgen): Update call to cgen.sh.
+ * Makefile.in: Regenerate
+
+end-sanitize-cygnus
+Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu"
+ instruction after the 4650's "mul" instruction; nobody's using the
+ 4010 these days. If object files someday indicate which processor
+ variant they're intended for, we can do a better job at this.
+
+start-sanitize-r5900
+Tue Jan 13 09:21:56 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (c.lt.s): Add r5900 variant.
+ (c.le.s): Likewise.
+
+end-sanitize-r5900
+Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MNEMONIC.
+ (cgen_parse_keyword): Rewrite.
+ * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MASK_BITSIZE.
+ * cgen-opc.c: Clean up pass over `struct foo' usage.
+ (cgen_keyword_lookup_value): Handle "" entry.
+ (cgen_keyword_add): Likewise.
+start-sanitize-cygnus
+ * Makefile.am: Add cgen support.
+ * Makefile.in: Regenerate.
+ * configure.in: Add cgen support.
+ * configure: Regenerate.
+ * aclocal.m4: Regenerate.
+ * cgen.sh, cgen-asm.in, cgen-dis.in: New files.
+end-sanitize-cygnus
+
+start-sanitize-sky
+Tue Jan 6 13:08:14 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c (print_insn_txvu): Handle no separator between
+ upper and lower insn #ifndef VERTICAL_BAR_SEPARATOR.
+
+Mon Jan 5 13:41:07 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c, txvu-opc.c: New files.
+ * configure.in: Compile them.
+ * configure: Regenerate.
+ * Makefile.am (ALL_MACHINES): Add txvu-{dis,opc}.lo.
+ (txvu-dis.lo,txvu-opc.lo): Add rules for.
+ * Makefile.in: Regenerate.
+
+Mon Dec 22 17:17:03 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure.in: Add txvu support.
+ * configure: Regenerate.
+ * disassemble.c: Add txvu support.
+
+end-sanitize-sky
+Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-opc.c: Add FP_D to s.d instruction flags.
+
+Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (halt, pulse): Enable them on the 68060.
+
+start-sanitize-tic80
+Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
+ PC relative offset forms before the 15 bit forms. An assembler command
+ line option now chooses the default.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Tue Dec 16 13:24:22 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c: Add many missing r5900 instructions.
+
+end-sanitize-r5900
+start-sanitize-r5900
+Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table): Set new flags bits
+ FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions.
+
+end-sanitize-r5900
+1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com>
+
+ * configure: Only build libopcodes shared if --enable-shared's value
+ was `yes', or was set to `*opcodes*'.
+ * aclocal.m4: Likewise.
+ * NOTE: this really needs to be fixed in libtool/libtool.m4, the
+ original source of this bit of code. It's not clear what the best fix
+ would be, though.
+
+start-sanitize-r5900
+Mon Dec 15 12:43:36 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.
+end-sanitize-r5900
+start-sanitize-tic80
+Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
+ (tic80_opcodes): Reorder table entries to put the 32 bit PC relative
+ offset forms before the 15 bit forms, to default to the long forms.
+
+end-sanitize-tic80
+Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
+
+Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (print_insn_little_arm): Prevent examination of stored
+ symbol if none is present.
+ (print_insn_big_arm): Prevent examination of stored symbol if
+ none is present.
+
+Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
+
+Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com>
+
+ * disassemble.c: Remove disasm_symaddr() function.
+
+ * arm-dis.c: Use info->symbol instead of info->flags to determine
+ if disassmbly should be in Thumb or Arm mode.
+
+Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c: Add support for disassembling Thumb opcodes.
+ (print_insn_thumb): New function.
+
+ * disassemble.c (disasm_symaddr): New function.
+
+ * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
+ (thumb_opcodes): Table of Thumb opcodes.
+
+Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (btst): Change Dd@s to Dd;b.
+
+ * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q',
+ and 'v' as operand types.
+
+Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add argument for lpstop. From Olivier Carmona
+ <olivier.carmona@di.epfl.ch>.
+ * m68k-dis.c (print_insn_m68k): Handle special case of lpstop,
+ which has a two word opcode with a one word argument.
+
+start-sanitize-d30v
+Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
+ unsigned, not signed.
+ (d30v_format_table): Add SHORT_CMPU cases for cmpu.
+
+end-sanitize-d30v
+start-sanitize-sh4
+Wed Nov 19 17:42:35 1997 Richard Henderson <rth@cygnus.com>
+
+ * sh-dis.c (print_insn_shx): Recognize all sh4 additions.
+ * sh-opc.h (fmov): Add @<REG_M>+,<DX_REG_N> variant for sh4.
+ (ftrv): Slay the cut-and-paste monster.
+
+end-sanitize-sh4
+Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-dis.c (print_operand):
+ Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
+
+Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-opc.c (OPERAND_FLAG): Split into:
+ (OPERAND_FFLAG, OPERAND_CFLAG) .
+ (FSRC): Split into:
+ (FFSRC, CFSRC).
+
+Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Move the INSN_MACRO ISA value to the membership
+ field for all INSN_MACRO's.
+ * mips16-opc.c: same
+
+Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (sync,cache): These are 3900 insns.
+
+Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ sh-opc.h (sh_table): Remove ftst/nan.
+
+start-sanitize-vr5400
+Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding.
+ (c.*.ob, mula.ob, mull.ob, muls.ob, mulsl.ob): Put 'k' version
+ last.
+ * mips-dis.c (print_insn_arg): Handle VR5400 operand types.
+
+end-sanitize-vr5400
+start-sanitize-tx49
+Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ Add tx49 insns and configury.
+
+end-sanitize-tx49
+Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (ffc, ffs): Fix mask.
+
+start-sanitize-d30v
+Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
+ control registers.
+
+end-sanitize-d30v
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+start-sanitize-vr5400
+ Added VR5400 instructions.
+ (N5): New cpu-id macro.
+end-sanitize-vr5400
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Replace // with /* ... */
+
Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com>
* sparc-opc.c: Add wr & rd for v9a asr's.
* v850-dis.c (v850_sreg_names): Use symbolic names for higher
system registers.
-start-sanitize-v850e
+end-sanitize-v850e
Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com>
* v850-opc.c: Fix typo in comment.
Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
- * configure (cgen_files): Add support for v850eq target.
- * configure.in (cgen_files): Add support for v850eq target.
+ * configure (cgen_files): Add support for v850ea target.
+ * configure.in (cgen_files): Add support for v850ea target.
end-sanitize-v850e
Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com>
Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com>
start-sanitize-v850e
- * v850-dis.c (disassemble): Add support for v850EQ instructions.
+ * v850-dis.c (disassemble): Add support for v850EA instructions.
* v850-opc.c (insert_i5div, extract_i5div): New Functions.
- (v850_opcodes): Add v850EQ instructions.
+ (v850_opcodes): Add v850EA instructions.
* v850-dis.c (disassemble): Add support for v850E instructions.
projects / deliverable / binutils-gdb.git / blobdiff