x86: allow suffix-less movzw and 64-bit movzb

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9ca0760accac3ee80af18f1b0f7bbd5d3ee16d46..109cb7f695650be670358d81f05029a3c4f4afa3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,127 @@
+2016-07-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
+       (movzb): Adjust to cover all permitted suffixes.
+       (movzw): New.
+       * i386-tbl.h: Re-generate.
+
+2016-07-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
+       (lgdt): Remove Tbyte from non-64-bit variant.
+       (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
+       xsaves64, xsavec64): Remove Disp16.
+       (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
+       Remove Disp32S from non-64-bit variants. Remove Disp16 from
+       64-bit variants.
+       (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
+       vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
+       vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
+       64-bit variants.
+       * i386-tbl.h: Re-generate.
+
+2016-07-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (xlat): Remove RepPrefixOk.
+       * i386-tbl.h: Re-generate.
+
+2016-06-30  Yao Qi  <yao.qi@linaro.org>
+
+       * arm-dis.c (print_insn): Fix typo in comment.
+
+2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-opc.c (operand_general_constraint_met_p): Check the
+       range of ldst_elemlist operands.
+       (print_register_list): Use PRIi64 to print the index.
+       (aarch64_print_operand): Likewise.
+
+2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
+
+       * mcore-opc.h: Remove sentinal.
+       * mcore-dis.c (print_insn_mcore): Adjust.
+
+2016-06-23  Graham Markall  <graham.markall@embecosm.com>
+
+       * arc-opc.c: Correct description of availability of NPS400
+       features.
+
+2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
+
+       * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
+       (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
+       mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
+       xor3>: New mnemonics.
+       <setb>: Change to a VX form instruction.
+       (insert_sh6): Add support for rldixor.
+       (extract_sh6): Likewise.
+
+2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
+
+       * arc-ext.h: Wrap in extern C.
+
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * arc-dis.c (arc_insn_length): Add comment on instruction length.
+       Use same method for determining instruction length on ARC700 and
+       NPS-400.
+       (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
+       * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
+       with the NPS400 subclass.
+       * arc-opc.c: Likewise.
+
+2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-opc.c (rdasr): New macro.
+       (wrasr): Likewise.
+       (rdpr): Likewise.
+       (wrpr): Likewise.
+       (rdhpr): Likewise.
+       (wrhpr): Likewise.
+       (sparc_opcodes): Use the macros above to fix and expand the
+       definition of read/write instructions from/to
+       asr/privileged/hyperprivileged instructions.
+       * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
+       %hva_mask_nz.  Prefer softint_set and softint_clear over
+       set_softint and clear_softint.
+       (print_insn_sparc): Support %ver in Rd.
+
+2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
+       architecture according to the hardware capabilities they require.
+
+2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
+       (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
+       bfd_mach_sparc_v9{c,d,e,v,m}.
+       * sparc-opc.c (MASK_V9C): Define.
+       (MASK_V9D): Likewise.
+       (MASK_V9E): Likewise.
+       (MASK_V9V): Likewise.
+       (MASK_V9M): Likewise.
+       (v6): Add MASK_V9{C,D,E,V,M}.
+       (v6notlet): Likewise.
+       (v7): Likewise.
+       (v8): Likewise.
+       (v9): Likewise.
+       (v9andleon): Likewise.
+       (v9a): Likewise.
+       (v9b): Likewise.
+       (v9c): Define.
+       (v9d): Likewise.
+       (v9e): Likewise.
+       (v9v): Likewise.
+       (v9m): Likewise.
+       (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
+
+2016-06-15  Nick Clifton  <nickc@redhat.com>
+
+       * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
+       constants to match expected behaviour.
+       (nds32_parse_opcode): Likewise.  Also for whitespace.
+
 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 
        * arc-opc.c (extract_rhv1): Extract value from insn.