-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (print_mips16_insn_arg): Simplify processing of
- extended operands.
- * mips16-opc.c (decode_mips16_operand): Switch the extended
- form of the `<' operand type to LSB position 22.
-
-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
- operand codes with `.' and `F' respectively.
- (mips16_opcodes): Likewise.
-
-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
- matching for INSN2_SHORT_ONLY opcode table entries.
- * mips16-opc.c (SH): New macro.
- (mips16_opcodes): Set SH in `pinfo2' for non-extensible
- instruction entries: "nop", "addu", "and", "break", "cmp",
- "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
- "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
- "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
- "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
- "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
- "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
- "seh", "sew", "zeb", "zeh", "zew" and "extend".
-
-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
- encoding support.
-
-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
- "extend".
-
-2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (set_default_mips_dis_options): Use
- HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
- call to `bfd_mips_elf_get_abiflags'.
- * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
- * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
- * config.in: Regenerate.
- * Makefile.in: Regenerate.
-
-2016-12-23 Tristan Gingold <gingold@adacore.com>
-
- * configure: Regenerate.
-
-2016-12-23 Tristan Gingold <gingold@adacore.com>
-
- * po/opcodes.pot: Regenerate.
-
-2016-12-21 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
-
-2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
- ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
- (print_insn_mips16): Check opcode entries for validity against
- the ISA level and ASE set selected.
-
-2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
- `insn' together, with `extend' as the high-order 16 bits.
- (match_kind): New enum.
- (print_insn_mips16): Rework for 32-bit instruction matching.
- Do not dump EXTEND prefixes here.
- * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
- Recode `match' and `mask' fields as 32-bit in absolute "jal" and
- "jalx" entries.
-
-2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
- than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
- INSN_MACRO entries.
-
-2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
- than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
- opcode).
-
-2016-12-20 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
- "*.aqrl".
-
-2016-12-20 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
- INSN_ALIAS.
-
-2016-12-20 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
- format.
+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_shorthands): New.
+ (opcode_modifiers): Replace Reg<N> with just Reg.
+ (set_bitfield_from_cpu_flag_init): Rename to
+ set_bitfield_from_shorthand. Drop value parameter. Process
+ operand_type_shorthands.
+ (set_bitfield): Adjust call accordingly.
+ * i386-opc.h (enum of operand types): Replace Reg<N> with just
+ Reg.
+ (union i386_operand_type): Replace reg<N> with just reg.
+ * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
+ vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
+ separate register and memory forms.
+ * i386-reg.tbl (al): Drop Byte.
+ (ax): Drop Word.
+ (eax): Drop Dword.
+ (rax): Drop Qword.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * disassemble.c (disassemble_init_for_target): Don't put PRU
+ between powerpc and rs6000 cases.
+
+2017-12-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
+ movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
+ sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
+ stos, sub, test, xor): Drop CheckRegSize from variants not
+ allowing for two (or more) register operands.
+ * i386-tbl.h: Re-generate.
-2016-12-20 Andrew Waterman <andrew@sifive.com>
+2017-12-13 Jim Wilson <jimw@sifive.com>
+
+ PR 22599
+ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
+
+2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * disassemble.c: Enable disassembler_needs_relocs for PRU.
+
+2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
+ Renlin Li <renlin.li@arm.com>
+
+ * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
+ (get_sym_code_type): Here.
+
+2017-12-03 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (extract_li20): Rewrite.
+
+2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
+ (operand_value_powerpc): Update return and argument type.
+ <value, top>: Update type.
+ (skip_optional_operands): Update argument type.
+ (lookup_powerpc): Likewise.
+ (lookup_vle): Likewise.
+ <table_opcd, table_mask, insn2>: Update type.
+ (lookup_spe2): Update argument type.
+ <table_opcd, table_mask, insn2>: Update type.
+ (print_insn_powerpc) <insn, value>: Update type.
+ Use PPC_INT_FMT for printing instructions and operands.
+ * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
+ insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
+ insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
+ extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
+ extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
+ insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
+ extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
+ insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
+ extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
+ insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
+ extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
+ insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
+ extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
+ insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
+ extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
+ insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
+ extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
+ insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
+ extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
+ extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
+ extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
+ insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
+ extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
+ insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
+ extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
+ extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
+ (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
+ BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
+ DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
+ SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
+ VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
+ VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
+ VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
+ XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
+ XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
+ XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
+ XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
+ New.
+ (output_cpu_flags): Update active_cpu_flags.
+ (process_i386_opcode_modifier): Update active_isstring.
+ (output_operand_type): Rename "macro" parameter to "stage",
+ changing its type.
+ (process_i386_operand_type): Likewise. Track presence of
+ BaseIndex and emit DispN accordingly.
+ (output_i386_opcode, process_i386_registers,
+ process_i386_initializers): Adjust calls to
+ process_i386_operand_type() for its changed parameter type.
+ * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
+ all insns operands having BaseIndex set.
+ * i386-tbl.h: Re-generate.
- * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
- XLEN when none is provided.
+2017-11-29 Jan Beulich <jbeulich@suse.com>
-2016-12-20 Andrew Waterman <andrew@sifive.com>
+ * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
+ entry.
+ (operand_types): Remove Vec_Disp8 entry.
+ * i386-opc.h (Vec_Disp8): Delete.
+ (union i386_operand_type): Remove vec_disp8.
+ (i386-opc.tbl): Remove Vec_Disp8.
+ * i386-init.h, i386-tbl.h: Re-generate.
- * riscv-opc.c: Formatting fixes.
+2017-11-29 Stefan Stroe <stroestefan@gmail.com>
-2016-12-20 Alan Modra <amodra@gmail.com>
+ * po/Make-in (datadir): Define as @datadir@.
+ (localedir): Define as @localedir@.
+ (gnulocaledir, gettextsrcdir): Use @datarootdir@.
- * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
- * Makefile.in: Regenerate.
- * po/POTFILES.in: Regenerate.
+2017-11-27 Nick Clifton <nickc@redhat.com>
-2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
+ * po/zh_CN.po: Updated simplified Chinese translation.
- * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
- Only examine ELF file structures here.
+2017-11-24 Jan Beulich <jbeulich@suse.com>
-2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
+ "df" groups.
- * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
- `bfd_mips_elf_get_abiflags' here.
+2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-2016-12-16 Nick Clifton <nickc@redhat.com>
+ * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
+ * i386-tbl.h: Regenerate.
- * arm-dis.c (print_insn_thumb32): Fix compile time warning
- computing value_in_comment.
+2017-11-23 Jan Beulich <jbeulich@suse.com>
-2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
+ the 16-bit addressing case.
- * mips-dis.c (mips_convert_abiflags_ases): New function.
- (set_default_mips_dis_options): Also infer ASE flags from ELF
- file structures.
+2017-11-23 Jan Beulich <jbeulich@suse.com>
-2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
+ (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
+ * i386-opc.tbl (ud1, ud2b): Add operands.
+ (ud0): New.
+ * i386-tbl.h: Re-generate.
- * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
- header flag interpretation code.
+2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
+ * i386-tbl.h: Regenerate.
- * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
- `pinfo2' with SP-relative "sd" entries.
+2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
+ * i386-tbl.h: Regenerate.
- * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
- compact jumps.
+2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
-2016-12-13 Renlin Li <renlin.li@arm.com>
+ *arc-opc (insert_rhv2): Check h-regs range.
- * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
- qualifier.
- (operand_general_constraint_met_p): Remove case for CP_REG.
- (aarch64_print_operand): Print CRn, CRm operand using imm field.
- * aarch64-tbl.h (QL_SYS): Use CR qualifier.
- (QL_SYSL): Likewise.
- (aarch64_opcode_table): Change CRn, CRm operand class and type.
- * aarch64-opc-2.c : Regenerate.
- * aarch64-asm-2.c : Likewise.
- * aarch64-dis-2.c : Likewise.
+2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
-2016-12-12 Yao Qi <yao.qi@linaro.org>
+ * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
+ * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
- * rx-dis.c: Include <setjmp.h>
- (struct private): New.
- (rx_get_byte): Check return value of read_memory_func, and
- call memory_error_func and OPCODES_SIGLONGJMP on error.
- (print_insn_rx): Call OPCODES_SIGSETJMP.
+2017-11-16 Tamar Christina <tamar.christina@arm.com>
-2016-12-12 Yao Qi <yao.qi@linaro.org>
+ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
+ and AARCH64_FEATURE_F16.
- * rl78-dis.c: Include <setjmp.h>.
- (struct private): New.
- (rl78_get_byte): Check return value of read_memory_func, and
- call memory_error_func and OPCODES_SIGLONGJMP on error.
- (print_insn_rl78_common): Call OPCODES_SIGJMP.
+2017-11-16 Tamar Christina <tamar.christina@arm.com>
-2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+ * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
+ (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
+ (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
+ (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
+ (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
+ (ldapur, ldapursw, stlur): New.
+ * aarch64-dis-2.c: Regenerate.
- * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
+2017-11-16 Jan Beulich <jbeulich@suse.com>
-2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+ (get_valid_dis386): Never flag bad opcode when
+ vex.register_specifier is beyond 7. Always store all four
+ bits of it. Move 16-/32-bit override in EVEX handling after
+ all to be overridden bits have been set.
+ (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
+ Use rex to determine GPR register set.
+ (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
+ OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
- * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
- than UINT.
+2017-11-15 Jan Beulich <jbeulich@suse.com>
-2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
+ determine GPR register set.
- * mips-dis.c (print_insn_mips16): Use a tab rather than a space
- to separate `extend' and its uninterpreted argument output.
- Separate hexadecimal halves of undecoded extended instructions
- output.
+2017-11-15 Jan Beulich <jbeulich@suse.com>
-2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
+ (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
+ (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
+ pass.
+ (OP_REG_VexI4): Drop low 4 bits check.
- * mips-dis.c (print_mips16_insn_arg): Remove extraneous
- indentation space across.
+2017-11-15 Jan Beulich <jbeulich@suse.com>
-2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-reg.tbl (axl): Remove Acc and Byte.
+ * i386-tbl.h: Re-generate.
- * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
- adjustment for PC-relative operations following MIPS16e compact
- jumps or undefined RR/J(AL)R(C) encodings.
+2017-11-14 Jan Beulich <jbeulich@suse.com>
-2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
+ (vex_len_table): Use VPCOM.
- * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
- variable to `reglane_index'.
+2017-11-14 Jan Beulich <jbeulich@suse.com>
-2016-12-08 Luis Machado <lgustavo@codesourcery.com>
+ * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
+ (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
+ * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
+ vpcmpw): Move up.
+ (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
+ vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
+ vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
+ vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
+ vpcmpnltuw): New.
+ * i386-tbl.h: Re-generate.
- * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
+2017-11-14 Jan Beulich <jbeulich@suse.com>
-2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
+ smov, ssca, stos, ssto, xlat): Drop Disp*.
+ * i386-tbl.h: Re-generate.
- * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
+2017-11-13 Jan Beulich <jbeulich@suse.com>
-2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+ * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
+ xsaveopt64): Add No_qSuf.
+ * i386-tbl.h: Re-generate.
- * mips16-opc.c (mips16_opcodes): Update comment naming structure
- members.
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
+ dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
+ cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
+ sder32_el2, vncr_el2.
+ (aarch64_sys_reg_supported_p): Likewise.
+ (aarch64_pstatefields): Add dit register.
+ (aarch64_pstatefield_supported_p): Likewise.
+ (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
+ vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
+ vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
+ rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
+ rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
+ ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
+ rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
+ (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
+ (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
+ (QL_STLW, QL_STLX): New.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.h (ins_addr_offset): New.
+ * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
+ (aarch64_ins_addr_offset): New.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_addr_offset): New.
+ * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
+ (aarch64_ext_addr_offset): New.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ * aarch64-opc.c (fields): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
+ (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+ AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
+ * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
+ * aarch64-tbl.h
+ (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h
+ (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
+ (aarch64_feature_sm4, aarch64_feature_sha3): New.
+ (aarch64_feature_fp_16_v8_2): New.
+ (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
+ (V8_4_INSN, CRYPTO_V8_2_INSN): New.
+ (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
+
+2017-11-08 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
+ (aarch64_feature_sha2, aarch64_feature_aes): New.
+ (SHA2, AES): New.
+ (AES_INSN, SHA2_INSN): New.
+ (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
+ (sha1h, sha1su1, sha256su0, sha1c, sha1p,
+ sha1m, sha1su0, sha256h, sha256h2, sha256su1):
+ Change to SHA2_INS.
+
+2017-11-08 Jiong Wang <jiong.wang@arm.com>
+ Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
+ FP16 instructions, including vfmal.f16 and vfmsl.f16.
+
+2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
+
+2017-11-07 Alan Modra <amodra@gmail.com>
+
+ * opintl.h: Formatting, comment fixes.
+ (gettext, ngettext): Redefine when ENABLE_NLS.
+ (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
+ (_): Define using gettext.
+ (textdomain, bindtextdomain): Use safer "do nothing".
+
+2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_hex): New variable.
+ (parse_option): Check for hex option.
+ (print_insn_arc): Use hexadecimal representation for short
+ immediate values when requested.
+ (print_arc_disassembler_options): Add hex option to the list.
+
+2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
+ (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
+ (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
+ (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
+ (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
+ (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
+ (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
+ (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
+ (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
+ (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
+ (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
+ (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
+ (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
+ (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
+ (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
+ (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
+ (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
+ (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
+ (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
+ Changed opcodes.
+ (prealloc, prefetch*): Place them before ld instruction.
+ * arc-opc.c (skip_this_opcode): Add ARITH class.
+
+2017-10-25 Alan Modra <amodra@gmail.com>
+
+ PR 22348
+ * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
+ (cr16_words, cr16_allWords, processing_argument_number): Likewise.
+ (imm4flag, size_changed): Likewise.
+ * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
+ (words, allWords, processing_argument_number): Likewise.
+ (cst4flag, size_changed): Likewise.
+ * crx-opc.c (crx_cst4_map): Rename from cst4_map.
+ (crx_cst4_maps): Rename from cst4_maps.
+ (crx_no_op_insn): Rename from no_op_insn.
+
+2017-10-24 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (match_c_addi16sp) : New function.
+ (match_c_addi4spn): New function.
+ (match_c_lui): Don't allow 0-immediate encodings.
+ (riscv_opcodes) <addi>: Use the above functions.
+ <add>: Likewise.
+ <c.addi4spn>: Likewise.
+ <c.addi16sp>: Likewise.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-init.h: Regenerate
+ * i386-tbl.h: Likewise
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
+ (enum): Add EVEX_W_0F3854_P_2.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
+ CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_BITALG.
+ * i386-opc.h (enum): Add CpuAVX512_BITALG.
+ (i386_cpu_flags): Add cpuavx512_bitalg..
+ * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
-2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
- * mips-dis.c (print_mips_disassembler_options): Reformat output.
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
+ CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VNNI.
+ * i386-opc.h (enum): Add CpuAVX512_VNNI.
+ (i386_cpu_flags): Add cpuavx512_vnni.
+ * i386-opc.tbl Add Intel AVX512_VNNI instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
-2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
+ (enum): Remove VEX_LEN_0F3A44_P_2.
+ (vex_len_table): Ditto.
+ (enum): Remove VEX_W_0F3A44_P_2.
+ (vew_w_table): Ditto.
+ (prefix_table): Adjust instructions (see prefixes above).
+ * i386-dis-evex.h (evex_table):
+ Add new instructions (see prefixes above).
+ * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
+ (bitfield_cpu_flags): Ditto.
+ * i386-opc.h (enum): Ditto.
+ (i386_cpu_flags): Ditto.
+ (CpuUnused): Comment out to avoid zero-width field problem.
+ * i386-opc.tbl (vpclmulqdq): New instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
- * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
- (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
+ PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
+ (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
+ VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
+ (vex_len_table): Ditto.
+ (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
+ VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
+ (vew_w_table): Ditto.
+ (prefix_table): Adjust instructions (see prefixes above).
+ * i386-dis-evex.h (evex_table):
+ Add new instructions (see prefixes above).
+ * i386-gen.c (cpu_flag_init): Add VAES.
+ (bitfield_cpu_flags): Ditto.
+ * i386-opc.h (enum): Ditto.
+ (i386_cpu_flags): Ditto.
+ * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
-2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
+ PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
+ PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
+ (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
+ EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
+ (prefix_table): Updated (see prefixes above).
+ (three_byte_table): Likewise.
+ (vex_w_table): Likewise.
+ * i386-dis-evex.h: Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
+ (cpu_flags): Add CpuGFNI.
+ * i386-opc.h (enum): Add CpuGFNI.
+ (i386_cpu_flags): Add cpugfni.
+ * i386-opc.tbl: Add Intel GFNI instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
- * arm-dis.c (coprocessor_opcodes): Add vjcvt.
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
+ Define EXbScalar and EXwScalar for OP_EX.
+ (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
+ PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
+ PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
+ PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
+ (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
+ EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
+ EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
+ EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
+ (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
+ (OP_E_memory): Likewise.
+ * i386-dis-evex.h: Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
+ CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VBMI2.
+ * i386-opc.h (enum): Add CpuAVX512_VBMI2.
+ (i386_cpu_flags): Add cpuavx512_vbmi2.
+ * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
-2016-12-01 Nick Clifton <nickc@redhat.com>
+2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
- PR binutils/20893
- * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
- opcode designator.
+ * visium-dis.c (disassem_class1) <case 0>: Print the operands.
-2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+2017-10-12 James Bowman <james.bowman@ftdichip.com>
- * arc-opc.c (insert_ra_chk): New function.
- (insert_rb_chk): Likewise.
- (insert_rad): Update text error message.
- (insert_rcd): Likewise.
- (insert_rhv2): Likewise.
+ * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
+ * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
+ K15. Add jmpix pattern.
+
+2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-opc.txt (prno, tpei, irbm): New instructions added.
+
+2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
+
+ * s390-opc.c (INSTR_SI_RD): New macro.
+ (INSTR_S_RD): Adjust example instruction.
+ * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
+ SI_RD.
+
+2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
+
+ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
+ e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
+ VLE multimple load/store instructions. Old e_ldm* variants are
+ kept as aliases.
+ Add missing e_lmvmcsrrw and e_stmvmcsrrw.
+
+2017-09-27 Nick Clifton <nickc@redhat.com>
+
+ PR 22179
+ * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
+ names for the fmv.x.s and fmv.s.x instructions respectively.
+
+2017-09-26 do <do@nerilex.org>
+
+ PR 22123
+ * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
+ be used on CPUs that have emacs support.
+
+2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
+
+ * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
+
+2017-09-09 Kamil Rytarowski <n54@gmx.com>
+
+ * nds32-asm.c: Rename __BIT() to N32_BIT().
+ * nds32-asm.h: Likewise.
+ * nds32-dis.c: Likewise.
+
+2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (last_active_prefix): Removed.
+ (ckprefix): Don't set last_active_prefix.
+ (NOTRACK_Fixup): Don't check last_active_prefix.
+
+2017-08-31 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2017-08-31 James Bowman <james.bowman@ftdichip.com>
+
+ * ft32-dis.c (print_insn_ft32): Correct display of non-address
+ fields.
+
+2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
+ PPC_OPCODE_EFS2 flag to "e200z4" entry.
+ New entries efs2 and spe2.
+ Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
+ (SPE2_OPCD_SEGS): New macro.
+ (spe2_opcd_indices): New.
+ (disassemble_init_powerpc): Handle SPE2 opcodes.
+ (lookup_spe2): New function.
+ (print_insn_powerpc): call lookup_spe2.
+ * ppc-opc.c (insert_evuimm1_ex0): New function.
+ (extract_evuimm1_ex0): Likewise.
+ (insert_evuimm_lt8): Likewise.
+ (extract_evuimm_lt8): Likewise.
+ (insert_off_spe2): Likewise.
+ (extract_off_spe2): Likewise.
+ (insert_Ddd): Likewise.
+ (extract_Ddd): Likewise.
+ (DD): New operand.
+ (EVUIMM_LT8): Likewise.
+ (EVUIMM_LT16): Adjust.
+ (MMMM): New operand.
+ (EVUIMM_1): Likewise.
+ (EVUIMM_1_EX0): Likewise.
+ (EVUIMM_2): Adjust.
+ (NNN): New operand.
+ (VX_OFF_SPE2): Likewise.
+ (BBB): Likewise.
+ (DDD): Likewise.
+ (VX_MASK_DDD): New mask.
+ (HH): New operand.
+ (VX_RA_CONST): New macro.
+ (VX_RA_CONST_MASK): Likewise.
+ (VX_RB_CONST): Likewise.
+ (VX_RB_CONST_MASK): Likewise.
+ (VX_OFF_SPE2_MASK): Likewise.
+ (VX_SPE_CRFD): Likewise.
+ (VX_SPE_CRFD_MASK VX): Likewise.
+ (VX_SPE2_CLR): Likewise.
+ (VX_SPE2_CLR_MASK): Likewise.
+ (VX_SPE2_SPLATB): Likewise.
+ (VX_SPE2_SPLATB_MASK): Likewise.
+ (VX_SPE2_OCTET): Likewise.
+ (VX_SPE2_OCTET_MASK): Likewise.
+ (VX_SPE2_DDHH): Likewise.
+ (VX_SPE2_DDHH_MASK): Likewise.
+ (VX_SPE2_HH): Likewise.
+ (VX_SPE2_HH_MASK): Likewise.
+ (VX_SPE2_EVMAR): Likewise.
+ (VX_SPE2_EVMAR_MASK): Likewise.
+ (PPCSPE2): Likewise.
+ (PPCEFS2): Likewise.
+ (vle_opcodes): Add EFS2 and some missing SPE opcodes.
+ (powerpc_macros): Map old SPE instructions have new names
+ with the same opcodes. Add SPE2 instructions which just are
+ mapped to SPE2.
+ (spe2_opcodes): Add SPE2 opcodes.
+
+2017-08-23 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c: Formatting and comment fixes. Move insert and
+ extract functions earlier, deleting forward declarations.
+ (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
+ RA_MASK.
+
+2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
+
+ * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
+
+2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * ppc-opc.c (insert_evuimm2_ex0): New function.
+ (extract_evuimm2_ex0): Likewise.
+ (insert_evuimm4_ex0): Likewise.
+ (extract_evuimm4_ex0): Likewise.
+ (insert_evuimm8_ex0): Likewise.
+ (extract_evuimm8_ex0): Likewise.
+ (insert_evuimm_lt16): Likewise.
+ (extract_evuimm_lt16): Likewise.
+ (insert_rD_rS_even): Likewise.
+ (extract_rD_rS_even): Likewise.
+ (insert_off_lsp): Likewise.
+ (extract_off_lsp): Likewise.
+ (RD_EVEN): New operand.
+ (RS_EVEN): Likewise.
+ (RSQ): Adjust.
+ (EVUIMM_LT16): New operand.
+ (HTM_SI): Adjust.
+ (EVUIMM_2_EX0): New operand.
+ (EVUIMM_4): Adjust.
+ (EVUIMM_4_EX0): New operand.
+ (EVUIMM_8): Adjust.
+ (EVUIMM_8_EX0): New operand.
+ (WS): Adjust.
+ (VX_OFF): New operand.
+ (VX_LSP): New macro.
+ (VX_LSP_MASK): Likewise.
+ (VX_LSP_OFF_MASK): Likewise.
+ (PPC_OPCODE_LSP): Likewise.
+ (vle_opcodes): Add LSP opcodes.
+ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
+
+2017-08-09 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
+ register operands in CRC instructions.
+ (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
+ comments.
+
+2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * disassemble.c (disassembler): Mark big and mach with
+ ATTRIBUTE_UNUSED.
+
+2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * disassemble.c (disassembler): Remove arch/mach/endian
+ assertions.
+
+2017-07-25 Nick Clifton <nickc@redhat.com>
+
+ PR 21739
+ * arc-opc.c (insert_rhv2): Use lower case first letter in error
+ message.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
+ (insert_r13el): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
- (insert_pcel): Likewise.
- (insert_nps_3bit_dst): Likewise.
- (insert_nps_3bit_dst_short): Likewise.
- (insert_nps_3bit_src2_short): Likewise.
+ (insert_pclel): Likewise.
(insert_nps_bitop_size_2b): Likewise.
- (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
- (RA_CHK): Define.
- (RB): Adjust.
- (RB_CHK): Define.
- (RC): Adjust.
- * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
- * arc-tbl.h (div, divu): All instructions are DIVREM class.
- Change first insn argument to check for LP_COUNT usage.
- (rem): Likewise.
- (ld, ldd): All instructions are LOAD class. Change first insn
- argument to check for LP_COUNT usage.
- (st, std): All instructions are STORE class.
- (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
- Change first insn argument to check for LP_COUNT usage.
- (mov): All instructions are MOVE class. Change first insn
- argument to check for LP_COUNT usage.
-
-2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (is_compatible_p): Remove function.
- (skip_this_opcode): Don't add any decoding class to decode list.
- Remove warning.
- (find_format_from_table): Go through all opcodes, and warn if we
- use a guessed mnemonic.
-
-2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
- Amit Pawar <amit.pawar@amd.com>
-
- PR binutils/20637
- * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
- instructions.
-
-2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
-
- * configure: Regenerate.
-
-2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-opc.c (HWS_V8): Definition moved from
- gas/config/tc-sparc.c.
- (HWS_V9): Likewise.
- (HWS_VA): Likewise.
- (HWS_VB): Likewise.
- (HWS_VC): Likewise.
- (HWS_VD): Likewise.
- (HWS_VE): Likewise.
- (HWS_VV): Likewise.
- (HWS_VM): Likewise.
- (HWS2_VM): Likewise.
- (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
- existing entries.
-
-2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
- instructions.
-
-2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
- (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
- (aarch64_opcode_table): Add fcmla and fcadd.
- (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
- * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
- * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
- * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
- * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
- * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
- * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
- (operand_general_constraint_met_p): Rotate and index range check.
- (aarch64_print_operand): Handle rotate operand.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Likewise.
- * aarch64-opc-2.c: Likewise.
-
-2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
- (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (QL_X1NIL): New.
- (arch64_opcode_table): Add ldraa, ldrab.
- (AARCH64_OPERANDS): Add "ADDR_SIMM10".
- * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
- * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
- * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
- * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
- * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
- * aarch64-opc.c (fields): Add data for FLD_S_simm10.
- (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
- (aarch64_print_operand): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
- brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (arch64_opcode_table): Add pacga.
- (AARCH64_OPERANDS): Add Rm_SP.
- * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
- autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
- autdzb, xpaci, xpacd.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
- apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
- apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
- (aarch64_sys_reg_supported_p): Add feature test for new registers.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
- (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
- autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
- autibsp.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
-
-2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20799
- * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
- * i386-dis.c (EdqwS): Removed.
- (dqw_swap_mode): Likewise.
- (intel_operand_size): Don't check dqw_swap_mode.
- (OP_E_register): Likewise.
- (OP_E_memory): Likewise.
- (OP_G): Likewise.
- (OP_EX): Likewise.
- * i386-opc.tbl: Remove "S" from EVEX vpextrw.
- * i386-tbl.h: Regerated.
-
-2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Merge AVX512F vmovq.
- * i386-tbl.h: Regerated.
-
-2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20701
- * i386-dis.c (THREE_BYTE_0F7A): Removed.
- (dis386_twobyte): Don't use THREE_BYTE_0F7A.
- (three_byte_table): Remove THREE_BYTE_0F7A.
-
-2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20775
- * i386-dis.c (FGRPd9_2): Replace 0 with 1.
- (FGRPd9_4): Replace 1 with 2.
- (FGRPd9_5): Replace 2 with 3.
- (FGRPd9_6): Replace 3 with 4.
- (FGRPd9_7): Replace 4 with 5.
- (FGRPda_5): Replace 5 with 6.
- (FGRPdb_4): Replace 6 with 7.
- (FGRPde_3): Replace 7 with 8.
- (FGRPdf_4): Replace 8 with 9.
- (fgrps): Add an entry for Bad_Opcode.
-
-2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-opc.c (arc_flag_operands): Add F_DI14.
- (arc_flag_classes): Add C_DI14.
- * arc-nps400-tbl.h: Add new exc instructions.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (arc_insn_length): Return length 8 for instructions with
- major opcode 0xa.
- * arc-nps-400-tbl.h: Add dcmac instruction.
- * arc-opc.c (arc_operands): Added operands for dcmac instruction.
- (insert_nps_rbdouble_64): Added.
- (extract_nps_rbdouble_64): Added.
- (insert_nps_proto_size): Added.
- (extract_nps_proto_size): Added.
-
-2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-dis.c (struct arc_operand_iterator): Remove all fields
- relating to long instruction processing, add new limm field.
- (OPCODE): Rename to...
- (OPCODE_32BIT_INSN): ...this.
- (OPCODE_AC): Delete.
- (skip_this_opcode): Handle different instruction lengths, update
- macro name.
- (special_flag_p): Update parameter type.
- (find_format_from_table): Update for more instruction lengths.
- (find_format_long_instructions): Delete.
- (find_format): Update for more instruction lengths.
- (arc_insn_length): Likewise.
- (extract_operand_value): Update for more instruction lengths.
- (operand_iterator_next): Remove code relating to long
- instructions.
- (arc_opcode_to_insn_type): New function.
- (print_insn_arc):Update for more instructions lengths.
- * arc-ext.c (extInstruction_t): Change argument type.
- * arc-ext.h (extInstruction_t): Change argument type.
- * arc-fxi.h: Change type unsigned to unsigned long long
- extensively throughout.
- * arc-nps400-tbl.h: Add long instructions taken from
- arc_long_opcodes table in arc-opc.c.
- * arc-opc.c: Update parameter types on insert/extract handlers.
- (arc_long_opcodes): Delete.
- (arc_num_long_opcodes): Delete.
- (arc_opcode_len): Update for more instruction lengths.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
- with arc_opcode_len.
- (find_format_long_instructions): Likewise.
- * arc-opc.c (arc_opcode_len): New function.
-
-2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Fix some instruction masks.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_82): Removed.
- (X86_64_82_REG_0): Likewise.
- (X86_64_82_REG_1): Likewise.
- (X86_64_82_REG_2): Likewise.
- (X86_64_82_REG_3): Likewise.
- (X86_64_82_REG_4): Likewise.
- (X86_64_82_REG_5): Likewise.
- (X86_64_82_REG_6): Likewise.
- (X86_64_82_REG_7): Likewise.
- (X86_64_82): New.
- (dis386): Use X86_64_82 instead of REG_82.
- (reg_table): Remove REG_82.
- (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
- X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
- X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
- X86_64_82_REG_7.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20754
- * i386-dis.c (REG_82): New.
- (X86_64_82_REG_0): Likewise.
- (X86_64_82_REG_1): Likewise.
- (X86_64_82_REG_2): Likewise.
- (X86_64_82_REG_3): Likewise.
- (X86_64_82_REG_4): Likewise.
- (X86_64_82_REG_5): Likewise.
- (X86_64_82_REG_6): Likewise.
- (X86_64_82_REG_7): Likewise.
- (dis386): Use REG_82.
- (reg_table): Add REG_82.
- (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
- X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
- X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_82): Renamed to ...
- (REG_83): This.
- (dis386): Updated.
- (reg_table): Likewise.
-
-2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
- CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_4VNNIW.
- * i386-opc.h (enum): (AVX512_4VNNIW): New.
- (i386_cpu_flags): Add cpuavx512_4vnniw.
- * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
- PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
- CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_4FMAPS.
- (opcode_modifiers): Add ImplicitQuadGroup modifier.
- * i386-opc.h (AVX512_4FMAP): New.
- (i386_cpu_flags): Add cpuavx512_4fmaps.
- (ImplicitQuadGroup): New.
- (i386_opcode_modifier): Add implicitquadgroup.
- * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
- Andrew Waterman <andrew@sifive.com>
-
- Add support for RISC-V architecture.
- * configure.ac: Add entry for bfd_riscv_arch.
- * configure: Regenerate.
- * disassemble.c (disassembler): Add support for riscv.
- (disassembler_usage): Likewise.
- * riscv-dis.c: New file.
- * riscv-opc.c: New file.
-
-2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
- (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
- (rm_table): Update the RM_0FAE_REG_7 entry.
- * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
- (cpu_flags): Remove CpuPCOMMIT.
- * i386-opc.h (CpuPCOMMIT): Removed.
- (i386_cpu_flags): Remove cpupcommit.
- * i386-opc.tbl: Remove pcommit.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20705
- * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
- the highest bit in VEX.vvvv for the 3-byte VEX prefix in
- 32-bit mode. Don't check vex.register_specifier in 32-bit
- mode.
- (OP_VEX): Check for invalid mask registers.
-
-2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20699
- * i386-dis.c (OP_E_memory): Check addr32flag in stead of
- sizeflag.
-
-2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20704
- * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
-
-2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
-
- * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
- local variable to `index_regno'.
-
-2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
-
- * arc-tbl.h: Removed any "inv.+" instructions from the table.
-
-2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
- usage on ISA basis.
-
-2016-10-11 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20666
- * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
-
-2016-10-07 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20667
- * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
- available.
-
-2016-10-07 Alan Modra <amodra@gmail.com>
-
- * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * aarch64-opc.c: Spell fall through comments consistently.
+ (insert_nps_imm_offset): Likewise.
+ (insert_nps_imm_entry): Likewise.
+ (insert_nps_size_16bit): Likewise.
+ (insert_nps_##NAME##_pos): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_bitop_ins_ext): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_min_hofs): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_rbdouble_64): Likewise.
+ (insert_nps_misc_imm_offset): Likewise.
+ * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
+ option description.
+
+2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
+ Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
+ correct the print.
+ * aarch64-dis-2.c: Regenerated.
+
+2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
+ table.
+
+2017-07-20 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h (sec_stat): New aux register.
+ (aux_kernel_sp): Likewise.
+ (aux_sec_u_sp): Likewise.
+ (aux_sec_k_sp): Likewise.
+ (sec_vecbase_build): Likewise.
+ (nsc_table_top): Likewise.
+ (nsc_table_base): Likewise.
+ (ersec_stat): Likewise.
+ (aux_sec_except): Likewise.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (extract_uimm12_20): New function.
+ (UIMM12_20): New operand.
+ (SIMM3_5_S): Adjust.
+ * arc-tbl.h (sjli): Add new instruction.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+ John Eric Martin <John.Martin@emmicro-us.com>
+
+ * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
+ (UIMM3_23): Adjust accordingly.
+ * arc-regs.h: Add/correct jli_base register.
+ * arc-tbl.h (jli_s): Likewise.
+
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * aarch64-opc.c: Fix spelling typos.
* i386-dis.c: Likewise.
- * aarch64-dis.c: Add missing fall through comments.
- * aarch64-opc.c: Likewise.
- * arc-dis.c: Likewise.
- * arm-dis.c: Likewise.
- * i386-dis.c: Likewise.
- * m68k-dis.c: Likewise.
- * mep-asm.c: Likewise.
- * ns32k-dis.c: Likewise.
- * sh-dis.c: Likewise.
- * tic4x-dis.c: Likewise.
- * tic6x-dis.c: Likewise.
- * vax-dis.c: Likewise.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * arc-ext.c (create_map): Add missing break.
- * msp430-decode.opc (encode_as): Likewise.
- * msp430-decode.c: Regenerate.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
- * crx-dis.c (print_insn_crx): Likewise.
-
-2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20657
- * i386-dis.c (putop): Don't assign alt twice.
-
-2016-09-29 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20553
- * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
-
-2016-09-29 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (L): Make compulsory.
- (LOPT): New, optional form of L.
- (HTM_R): Define as LOPT.
- (L0, L1): Delete.
- (L32OPT): New, optional for 32-bit L.
- (L2OPT): New, 2-bit L for dcbf.
- (SVC_LEC): Update.
- (L2): Define.
- (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
- (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
- <dcbf>: Use L2OPT.
- <tlbiel, tlbie>: Use LOPT.
- <wclr, wclrall>: Use L2.
-
-2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
-
- * Makefile.in: Regenerate.
- * configure: Likewise.
-
-2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-ext-tbl.h (EXTINSN2OPF): Define.
- (EXTINSN2OP): Use EXTINSN2OPF.
- (bspeekm, bspop, modapp): New extension instructions.
- * arc-opc.c (F_DNZ_ND): Define.
- (F_DNZ_D): Likewise.
- (F_SIZEB1): Changed.
- (C_DNZ_D): Define.
- (C_HARD): Changed.
- * arc-tbl.h (dbnz): New instruction.
- (prealloc): Allow it for ARC EM.
- (xbfu): Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (print_immediate_offset_address): Print spaces
- after commas in addresses.
- (aarch64_print_operand): Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
- rather than "should be" or "expected to be" in error messages.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-dis.c (remove_dot_suffix): New function, split out from...
- (print_mnemonic_name): ...here.
- (print_comment): New function.
- (print_aarch64_insn): Call it.
- * aarch64-opc.c (aarch64_conds): Add SVE names.
- (aarch64_print_operand): Print alternative condition names in
- a comment.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
- (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
- (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
- (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
- (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
- (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
- (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
- (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
- (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
- (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
- (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
- (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
- (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
- (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
- (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
- (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
- (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
- (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
- (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
- (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
- (OP_SVE_XWU, OP_SVE_XXU): New macros.
- (aarch64_feature_sve): New variable.
- (SVE): New macro.
- (_SVE_INSN): Likewise.
- (aarch64_opcode_table): Add SVE instructions.
- * aarch64-opc.h (extract_fields): Declare.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.c (extract_fields): Make global.
- (do_misc_decoding): Handle the new SVE aarch64_ops.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
- (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
- aarch64_field_kinds.
- * aarch64-opc.c (fields): Add corresponding entries.
- * aarch64-asm.c (aarch64_get_variant): New function.
- (aarch64_encode_variant_using_iclass): Likewise.
- (aarch64_opcode_encode): Call it.
- * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
- (aarch64_opcode_decode): Call it.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
- and FP register operands.
- * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
- (FLD_SVE_Vn): New aarch64_field_kinds.
- * aarch64-opc.c (fields): Add corresponding entries.
- (aarch64_print_operand): Handle the new SVE core and FP register
- operands.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm-2.c: Likewise.
- * aarch64-dis-2.c: Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
- immediate operands.
- * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
- * aarch64-opc.c (fields): Add corresponding entry.
- (operand_general_constraint_met_p): Handle the new SVE FP immediate
- operands.
- (aarch64_print_operand): Likewise.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
- (ins_sve_float_zero_one): New inserters.
- * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
- (aarch64_ins_sve_float_half_two): Likewise.
- (aarch64_ins_sve_float_zero_one): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
- (ext_sve_float_zero_one): New extractors.
- * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
- (aarch64_ext_sve_float_half_two): Likewise.
- (aarch64_ext_sve_float_zero_one): Likewise.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
- integer immediate operands.
- * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
- (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
- (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
- * aarch64-opc.c (fields): Add corresponding entries.
- (operand_general_constraint_met_p): Handle the new SVE integer
- immediate operands.
- (aarch64_print_operand): Likewise.
- (aarch64_sve_dupm_mov_immediate_p): New function.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
- (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
- * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
- (aarch64_ins_limm): ...here.
- (aarch64_ins_inv_limm): New function.
- (aarch64_ins_sve_aimm): Likewise.
- (aarch64_ins_sve_asimm): Likewise.
- (aarch64_ins_sve_limm_mov): Likewise.
- (aarch64_ins_sve_shlimm): Likewise.
- (aarch64_ins_sve_shrimm): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
- (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
- * aarch64-dis.c (decode_limm): New function, split out from...
- (aarch64_ext_limm): ...here.
- (aarch64_ext_inv_limm): New function.
- (decode_sve_aimm): Likewise.
- (aarch64_ext_sve_aimm): Likewise.
- (aarch64_ext_sve_asimm): Likewise.
- (aarch64_ext_sve_limm_mov): Likewise.
- (aarch64_top_bit): Likewise.
- (aarch64_ext_sve_shlimm): Likewise.
- (aarch64_ext_sve_shrimm): Likewise.
- * aarch64-dis-2.c: Regenerate.
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
- operands.
- * aarch64-opc.c (aarch64_operand_modifiers): Initialize
- the AARCH64_MOD_MUL_VL entry.
- (value_aligned_p): Cope with non-power-of-two alignments.
- (operand_general_constraint_met_p): Handle the new MUL VL addresses.
- (print_immediate_offset_address): Likewise.
- (aarch64_print_operand): Likewise.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
- (ins_sve_addr_ri_s9xvl): New inserters.
- * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
- (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
- (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
- (ext_sve_addr_ri_s9xvl): New extractors.
- * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
- (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
- (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
- (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
- address operands.
- * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
- (FLD_SVE_xs_22): New aarch64_field_kinds.
- (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
- (get_operand_specific_data): New function.
- * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
- FLD_SVE_xs_14 and FLD_SVE_xs_22.
- (operand_general_constraint_met_p): Handle the new SVE address
- operands.
- (sve_reg): New array.
- (get_addr_sve_reg_name): New function.
- (aarch64_print_operand): Handle the new SVE address operands.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
- (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
- (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
- * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
- (aarch64_ins_sve_addr_rr_lsl): Likewise.
- (aarch64_ins_sve_addr_rz_xtw): Likewise.
- (aarch64_ins_sve_addr_zi_u5): Likewise.
- (aarch64_ins_sve_addr_zz): Likewise.
- (aarch64_ins_sve_addr_zz_lsl): Likewise.
- (aarch64_ins_sve_addr_zz_sxtw): Likewise.
- (aarch64_ins_sve_addr_zz_uxtw): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
- (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
- (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
- * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
- (aarch64_ext_sve_addr_ri_u6): Likewise.
- (aarch64_ext_sve_addr_rr_lsl): Likewise.
- (aarch64_ext_sve_addr_rz_xtw): Likewise.
- (aarch64_ext_sve_addr_zi_u5): Likewise.
- (aarch64_ext_sve_addr_zz): Likewise.
- (aarch64_ext_sve_addr_zz_lsl): Likewise.
- (aarch64_ext_sve_addr_zz_sxtw): Likewise.
- (aarch64_ext_sve_addr_zz_uxtw): Likewise.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
- AARCH64_OPND_SVE_PATTERN_SCALED.
- * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
- * aarch64-opc.c (fields): Add a corresponding entry.
- (set_multiplier_out_of_range_error): New function.
- (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
- (operand_general_constraint_met_p): Handle
- AARCH64_OPND_SVE_PATTERN_SCALED.
- (print_register_offset_address): Use PRIi64 to print the
- shift amount.
- (aarch64_print_operand): Likewise. Handle
- AARCH64_OPND_SVE_PATTERN_SCALED.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_sve_scale): New inserter.
- * aarch64-asm.c (aarch64_ins_sve_scale): New function.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_scale): New inserter.
- * aarch64-dis.c (aarch64_ext_sve_scale): New function.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
- AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
- * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
- (FLD_SVE_prfop): Likewise.
- * aarch64-opc.c: Include libiberty.h.
- (aarch64_sve_pattern_array): New variable.
- (aarch64_sve_prfop_array): Likewise.
- (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
- (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
- AARCH64_OPND_SVE_PRFOP.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Likewise.
- * aarch64-opc-2.c: Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
- AARCH64_OPND_QLF_P_[ZM].
- (aarch64_print_operand): Print /z and /m where appropriate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
- * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
- (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
- (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
- (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
- * aarch64-opc.c (fields): Add corresponding entries here.
- (operand_general_constraint_met_p): Check that SVE register lists
- have the correct length. Check the ranges of SVE index registers.
- Check for cases where p8-p15 are used in 3-bit predicate fields.
- (aarch64_print_operand): Handle the new SVE operands.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
- * aarch64-asm.c (aarch64_ins_sve_index): New function.
- (aarch64_ins_sve_reglist): Likewise.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
- * aarch64-dis.c (aarch64_ext_sve_index): New function.
- (aarch64_ext_sve_reglist): Likewise.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
- (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
- (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
- * aarch64-opc.c (aarch64_match_operands_constraint): Check for
- tied operands.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (get_offset_int_reg_name): New function.
- (print_immediate_offset_address): Likewise.
- (print_register_offset_address): Take the base and offset
- registers as parameters.
- (aarch64_print_operand): Update caller accordingly. Use
- print_immediate_offset_address.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (BANK): New macro.
- (R32, R64): Take a register number as argument
- (int_reg): Use BANK.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (print_register_list): Add a prefix parameter.
- (aarch64_print_operand): Update accordingly.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
- for FPIMM.
- * aarch64-asm.h (ins_fpimm): New inserter.
- * aarch64-asm.c (aarch64_ins_fpimm): New function.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_fpimm): New extractor.
- * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
- (aarch64_ext_fpimm): New function.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-asm.c: Include libiberty.h.
- (insert_fields): New function.
- (aarch64_ins_imm): Use it.
- * aarch64-dis.c (extract_fields): New function.
- (aarch64_ext_imm): Use it.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
- with an esize parameter.
- (operand_general_constraint_met_p): Update accordingly.
- Fix misindented code.
- * aarch64-asm.c (aarch64_ins_limm): Update call to
- aarch64_logical_immediate_p.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
-
-2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (find_format): Walk the linked list pointed by einsn.
-
-2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
- <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
- xor3>: Delete mnemonics.
- <cp_abort>: Rename mnemonic from ...
- <cpabort>: ...to this.
- <setb>: Change to a X form instruction.
- <sync>: Change to 1 operand form.
- <copy>: Delete mnemonic.
- <copy_first>: Rename mnemonic from ...
- <copy>: ...to this.
- <paste, paste.>: Delete mnemonics.
- <paste_last>: Rename mnemonic from ...
- <paste.>: ...to this.
-
-2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
-
- * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
-
-2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-
- * s390-mkopc.c (main): Support alternate arch strings.
-
-2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
-
- * s390-opc.txt: Fix kmctr instruction type.
-
-2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
- * i386-init.h: Regenerated.
-
-2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
-
- * opcodes/arc-dis.c (print_insn_arc): Changed.
-
-2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
- camellia_fl.
-
-2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
-
- * arm-dis.c (psr_name): Use hex as case labels. Add detection for
- MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
- FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
-
-2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
- (PREFIX_MOD_3_0FAE_REG_4): Likewise.
- (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
- PREFIX_MOD_3_0FAE_REG_4.
- (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
- PREFIX_MOD_3_0FAE_REG_4.
- * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
- (cpu_flags): Add CpuPTWRITE.
- * i386-opc.h (CpuPTWRITE): New.
- (i386_cpu_flags): Add cpuptwrite.
- * i386-opc.tbl: Add ptwrite instruction.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
-
- * arc-dis.h: Wrap around in extern "C".
-
-2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (V8_2_INSN): New macro.
- (aarch64_opcode_table): Use it.
-
-2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Make more use of
- CORE_INSN, __FP_INSN and SIMD_INSN.
-
-2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
- (aarch64_opcode_table): Update uses accordingly.
-
-2016-07-25 Andrew Jenner <andrew@codesourcery.com>
- Kwok Cheung Yeung <kcy@codesourcery.com>
-
- opcodes/
- * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
- 'e_cmplwi' to 'e_cmpli' instead.
- (OPVUPRT, OPVUPRT_MASK): Define.
- (powerpc_opcodes): Add E200Z4 insns.
- (vle_opcodes): Add context save/restore insns.
-
-2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
-
- * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
- "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
- "j".
-
-2016-07-27 Graham Markall <graham.markall@embecosm.com>
-
- * arc-nps400-tbl.h: Change block comments to GNU format.
- * arc-dis.c: Add new globals addrtypenames,
- addrtypenames_max, and addtypeunknown.
- (get_addrtype): New function.
- (print_insn_arc): Print colons and address types when
- required.
- * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
- define insert and extract functions for all address types.
- (arc_operands): Add operands for colon and all address
- types.
- * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
- * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
- insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
- * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
- * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
- insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
-
-2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * configure: Regenerated.
+2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+
+ * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
+ max_addr_offset and octets variables to size_t.
+
+2017-07-12 Alan Modra <amodra@gmail.com>
+
+ * po/da.po: Update from translationproject.org/latest/opcodes/.
+ * po/de.po: Likewise.
+ * po/es.po: Likewise.
+ * po/fi.po: Likewise.
+ * po/fr.po: Likewise.
+ * po/id.po: Likewise.
+ * po/it.po: Likewise.
+ * po/nl.po: Likewise.
+ * po/pt_BR.po: Likewise.
+ * po/ro.po: Likewise.
+ * po/sv.po: Likewise.
+ * po/tr.po: Likewise.
+ * po/uk.po: Likewise.
+ * po/vi.po: Likewise.
+ * po/zh_CN.po: Likewise.
+
+2017-07-11 Yao Qi <yao.qi@linaro.org>
+ Alan Modra <amodra@gmail.com>
+
+ * cgen.sh: Mark generated files read-only.
+ * epiphany-asm.c: Regenerate.
+ * epiphany-desc.c: Regenerate.
+ * epiphany-desc.h: Regenerate.
+ * epiphany-dis.c: Regenerate.
+ * epiphany-ibld.c: Regenerate.
+ * epiphany-opc.c: Regenerate.
+ * epiphany-opc.h: Regenerate.
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * fr30-desc.h: Regenerate.
+ * fr30-dis.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * fr30-opc.c: Regenerate.
+ * fr30-opc.h: Regenerate.
+ * frv-asm.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * frv-desc.h: Regenerate.
+ * frv-dis.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * frv-opc.c: Regenerate.
+ * frv-opc.h: Regenerate.
+ * ip2k-asm.c: Regenerate.
+ * ip2k-desc.c: Regenerate.
+ * ip2k-desc.h: Regenerate.
+ * ip2k-dis.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * ip2k-opc.c: Regenerate.
+ * ip2k-opc.h: Regenerate.
+ * iq2000-asm.c: Regenerate.
+ * iq2000-desc.c: Regenerate.
+ * iq2000-desc.h: Regenerate.
+ * iq2000-dis.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * iq2000-opc.c: Regenerate.
+ * iq2000-opc.h: Regenerate.
+ * lm32-asm.c: Regenerate.
+ * lm32-desc.c: Regenerate.
+ * lm32-desc.h: Regenerate.
+ * lm32-dis.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * lm32-opc.c: Regenerate.
+ * lm32-opc.h: Regenerate.
+ * lm32-opinst.c: Regenerate.
+ * m32c-asm.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32c-desc.h: Regenerate.
+ * m32c-dis.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32c-opc.c: Regenerate.
+ * m32c-opc.h: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
+ * m32r-opinst.c: Regenerate.
+ * mep-asm.c: Regenerate.
+ * mep-desc.c: Regenerate.
+ * mep-desc.h: Regenerate.
+ * mep-dis.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mep-opc.c: Regenerate.
+ * mep-opc.h: Regenerate.
+ * mt-asm.c: Regenerate.
+ * mt-desc.c: Regenerate.
+ * mt-desc.h: Regenerate.
+ * mt-dis.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * mt-opc.c: Regenerate.
+ * mt-opc.h: Regenerate.
+ * or1k-asm.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * or1k-desc.h: Regenerate.
+ * or1k-dis.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * or1k-opc.c: Regenerate.
+ * or1k-opc.h: Regenerate.
+ * or1k-opinst.c: Regenerate.
+ * xc16x-asm.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xc16x-desc.h: Regenerate.
+ * xc16x-dis.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xc16x-opc.c: Regenerate.
+ * xc16x-opc.h: Regenerate.
+ * xstormy16-asm.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
+ * xstormy16-desc.h: Regenerate.
+ * xstormy16-dis.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+ * xstormy16-opc.c: Regenerate.
+ * xstormy16-opc.h: Regenerate.
-2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
+2017-07-07 Alan Modra <amodra@gmail.com>
- * arc-dis.c (skipclass): New structure.
- (decodelist): New variable.
- (is_compatible_p): New function.
- (new_element): Likewise.
- (skip_class_p): Likewise.
- (find_format_from_table): Use skip_class_p function.
- (find_format): Decode first the extension instructions.
- (print_insn_arc): Select either ARCEM or ARCHS based on elf
- e_flags.
- (parse_option): New function.
- (parse_disassembler_options): Likewise.
- (print_arc_disassembler_options): Likewise.
- (print_insn_arc): Use parse_disassembler_options function. Proper
- select ARCv2 cpu variant.
- * disassemble.c (disassembler_usage): Add ARC disassembler
- options.
+ * cgen-dis.in: Include disassemble.h, not dis-asm.h.
+ * m32c-dis.c: Regenerate.
+ * mep-dis.c: Regenerate.
-2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
+2017-07-05 Borislav Petkov <bp@suse.de>
- * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
- annotation from the "nal" entry and reorder it beyond "bltzal".
+ * i386-dis.c: Enable ModRM.reg /6 aliases.
-2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
+2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
- * sparc-opc.c (ldtxa): New macro.
- (sparc_opcodes): Use the macro defined above to add entries for
- the LDTXA instructions.
- (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
- instruction.
+ * opcodes/arm-dis.c: Support MVFR2 in disassembly
+ with vmrs and vmsr.
-2016-07-07 James Bowman <james.bowman@ftdichip.com>
+2017-07-04 Tristan Gingold <gingold@adacore.com>
- * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
- and "jmpc".
+ * configure: Regenerate.
-2016-07-01 Jan Beulich <jbeulich@suse.com>
+2017-07-03 Tristan Gingold <gingold@adacore.com>
- * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
- (movzb): Adjust to cover all permitted suffixes.
- (movzw): New.
- * i386-tbl.h: Re-generate.
+ * po/opcodes.pot: Regenerate.
-2016-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
- (lgdt): Remove Tbyte from non-64-bit variant.
- (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
- xsaves64, xsavec64): Remove Disp16.
- (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
- Remove Disp32S from non-64-bit variants. Remove Disp16 from
- 64-bit variants.
- (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
- vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
- vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
- 64-bit variants.
- * i386-tbl.h: Re-generate.
+2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
+ entries to the MSA ASE instruction block.
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
+ * micromips-opc.c (XPA, XPAVZ): New macros.
+ (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
+ "mthgc0".
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
+ * micromips-opc.c (I36): New macro.
+ (micromips_opcodes): Add "eretnc".
+
+2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+ Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): Handle the
+ ASE_XPA_VIRT flag.
+ (parse_mips_ase_option): New function.
+ (parse_mips_dis_option): Factor out ASE option handling to the
+ new function. Call `mips_calculate_combination_ases'.
+ * mips-opc.c (XPAVZ): New macro.
+ (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
+ "mfhgc0", "mthc0" and "mthgc0".
+
+2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): New function.
+ (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
+ calculation to the new function.
+ (set_default_mips_dis_options): Call the new function.
+
+2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (parse_disassembler_options): Use
+ FOR_EACH_DISASSEMBLER_OPTION.
+
+2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
+ disassembler option strings.
+ (parse_cpu_option): Likewise.
+
+2017-06-28 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
+ * aarch64-dis.c (aarch64_ext_reglane): Likewise.
+ * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
+ (aarch64_feature_dotprod, DOT_INSN): New.
+ (udot, sdot): New.
+ * aarch64-dis-2.c: Regenerated.
+
+2017-06-28 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
+
+2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+ Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-formats.h (INT_BIAS): New macro.
+ (INT_ADJ): Redefine in INT_BIAS terms.
+ * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
+ (mips_print_save_restore): New function.
+ (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
+ (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
+ call.
+ (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
+ (print_mips16_insn_arg): Call `mips_print_save_restore' for
+ OP_SAVE_RESTORE_LIST handling, factored out from here.
+ * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
+ (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
+ (mips_builtin_opcodes): Add "restore" and "save" entries.
+ * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
+ (IAMR2): New macro.
+ (mips16_opcodes): Add "copyw" and "ucopyw" entries.
+
+2017-06-23 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
+ alias; do not mark SLTI instruction as an alias.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (RM_0FAE_REG_5): Removed.
+ (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
+ (PREFIX_MOD_3_0FAE_REG_5): Likewise.
+ (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
+ PREFIX_MOD_3_0F01_REG_5_RM_0.
+ (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
+ PREFIX_MOD_3_0FAE_REG_5.
+ (mod_table): Update MOD_0FAE_REG_5.
+ (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
+ * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
+ * i386-tbl.h: Regenerated.
-2016-07-01 Jan Beulich <jbeulich@suse.com>
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
- * i386-opc.tbl (xlat): Remove RepPrefixOk.
- * i386-tbl.h: Re-generate.
+ * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
-2016-06-30 Yao Qi <yao.qi@linaro.org>
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
- * arm-dis.c (print_insn): Fix typo in comment.
+ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
+ and "jmp{&|}".
+ (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
+ prefix.
-2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
+2017-06-19 Nick Clifton <nickc@redhat.com>
- * aarch64-opc.c (operand_general_constraint_met_p): Check the
- range of ldst_elemlist operands.
- (print_register_list): Use PRIi64 to print the index.
- (aarch64_print_operand): Likewise.
+ PR binutils/21614
+ * score-dis.c (score_opcodes): Add sentinel.
-2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+2017-06-16 Alan Modra <amodra@gmail.com>
- * mcore-opc.h: Remove sentinal.
- * mcore-dis.c (print_insn_mcore): Adjust.
+ * rx-decode.c: Regenerate.
-2016-06-23 Graham Markall <graham.markall@embecosm.com>
+2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
- * arc-opc.c: Correct description of availability of NPS400
- features.
+ PR binutils/21594
+ * i386-dis.c (OP_E_register): Check valid bnd register.
+ (OP_G): Likewise.
-2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
+2017-06-15 Nick Clifton <nickc@redhat.com>
- * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
- (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
- mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
- xor3>: New mnemonics.
- <setb>: Change to a VX form instruction.
- (insert_sh6): Add support for rldixor.
- (extract_sh6): Likewise.
+ PR binutils/21595
+ * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
+ range value.
-2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+2017-06-15 Nick Clifton <nickc@redhat.com>
- * arc-ext.h: Wrap in extern C.
+ PR binutils/21588
+ * rl78-decode.opc (OP_BUF_LEN): Define.
+ (GETBYTE): Check for the index exceeding OP_BUF_LEN.
+ (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
+ array.
+ * rl78-decode.c: Regenerate.
-2016-06-21 Graham Markall <graham.markall@embecosm.com>
+2017-06-15 Nick Clifton <nickc@redhat.com>
- * arc-dis.c (arc_insn_length): Add comment on instruction length.
- Use same method for determining instruction length on ARC700 and
- NPS-400.
- (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
- * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
- with the NPS400 subclass.
- * arc-opc.c: Likewise.
+ PR binutils/21586
+ * bfin-dis.c (gregs): Clip index to prevent overflow.
+ (regs): Likewise.
+ (regs_lo): Likewise.
+ (regs_hi): Likewise.
-2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+2017-06-14 Nick Clifton <nickc@redhat.com>
- * sparc-opc.c (rdasr): New macro.
- (wrasr): Likewise.
- (rdpr): Likewise.
- (wrpr): Likewise.
- (rdhpr): Likewise.
- (wrhpr): Likewise.
- (sparc_opcodes): Use the macros above to fix and expand the
- definition of read/write instructions from/to
- asr/privileged/hyperprivileged instructions.
- * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
- %hva_mask_nz. Prefer softint_set and softint_clear over
- set_softint and clear_softint.
- (print_insn_sparc): Support %ver in Rd.
+ PR binutils/21576
+ * score7-dis.c (score_opcodes): Add sentinel.
-2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+2017-06-14 Yao Qi <yao.qi@linaro.org>
- * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
- architecture according to the hardware capabilities they require.
+ * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
+ * arm-dis.c: Likewise.
+ * ia64-dis.c: Likewise.
+ * mips-dis.c: Likewise.
+ * spu-dis.c: Likewise.
+ * disassemble.h (print_insn_aarch64): New declaration, moved from
+ include/dis-asm.h.
+ (print_insn_big_arm, print_insn_big_mips): Likewise.
+ (print_insn_i386, print_insn_ia64): Likewise.
+ (print_insn_little_arm, print_insn_little_mips): Likewise.
+
+2017-06-14 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21587
+ * rx-decode.opc: Include libiberty.h
+ (GET_SCALE): New macro - validates access to SCALE array.
+ (GET_PSCALE): New macro - validates access to PSCALE array.
+ (DIs, SIs, S2Is, rx_disp): Use new macros.
+ * rx-decode.c: Regenerate.
+
+2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
+
+2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
+
+ * arc-dis.c (enforced_isa_mask): Declare.
+ (cpu_types): Likewise.
+ (parse_cpu_option): New function.
+ (parse_disassembler_options): Use it.
+ (print_insn_arc): Use enforced_isa_mask.
+ (print_arc_disassembler_options): Document new options.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * alpha-dis.c: Include disassemble.h, don't include
+ dis-asm.h.
+ * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
+ * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
+ * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
+ * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
+ * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
+ * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
+ * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
+ * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
+ * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
+ * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
+ * moxie-dis.c, msp430-dis.c, mt-dis.c:
+ * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
+ * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
+ * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
+ * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
+ * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
+ * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
+ * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
+ * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
+ * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
+ * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
+ * z80-dis.c, z8k-dis.c: Likewise.
+ * disassemble.h: New file.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * rl78-dis.c (rl78_get_disassembler): If parameter abfd
+ is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * disassemble.c (disassembler): Add arguments a, big and mach.
+ Use them.
+
+2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (NOTRACK_Fixup): New.
+ (NOTRACK): Likewise.
+ (NOTRACK_PREFIX): Likewise.
+ (last_active_prefix): Likewise.
+ (reg_table): Use NOTRACK on indirect call and jmp.
+ (ckprefix): Set last_active_prefix.
+ (prefix_name): Return "notrack" for NOTRACK_PREFIX.
+ * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
+ * i386-opc.h (NoTrackPrefixOk): New.
+ (i386_opcode_modifier): Add notrackprefixok.
+ * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
+ Add notrack.
+ * i386-tbl.h: Regenerated.
-2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
- * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
- (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
- bfd_mach_sparc_v9{c,d,e,v,m}.
- * sparc-opc.c (MASK_V9C): Define.
- (MASK_V9D): Likewise.
- (MASK_V9E): Likewise.
- (MASK_V9V): Likewise.
- (MASK_V9M): Likewise.
- (v6): Add MASK_V9{C,D,E,V,M}.
+ * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
+ (X_IMM2): Define.
+ (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
+ bfd_mach_sparc_v9m8.
+ (print_insn_sparc): Handle new operand types.
+ * sparc-opc.c (MASK_M8): Define.
+ (v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
- (v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
- (v9c): Define.
+ (v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
- (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
-
-2016-06-15 Nick Clifton <nickc@redhat.com>
-
- * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
- constants to match expected behaviour.
- (nds32_parse_opcode): Likewise. Also for whitespace.
-
-2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-opc.c (extract_rhv1): Extract value from insn.
-
-2016-06-14 Graham Markall <graham.markall@embecosm.com>
-
- * arc-nps400-tbl.h: Add ldbit instruction.
- * arc-opc.c: Add flag classes required for ldbit.
+ (v9andleon): Likewise.
+ (m8): Define.
+ (HWS_VM8): Define.
+ (HWS2_VM8): Likewise.
+ (sparc_opcode_archs): Add entry for "m8".
+ (sparc_opcodes): Add OSA2017 and M8 instructions
+ dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
+ fpx{ll,ra,rl}64x,
+ ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
+ ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
+ revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
+ stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
+ (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
+ ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
+ ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
+ ASI_CORE_SELECT_COMMIT_NHT.
+
+2017-05-18 Alan Modra <amodra@gmail.com>
+
+ * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
+ * aarch64-dis.c: Likewise.
+ * aarch64-gen.c: Likewise.
+ * aarch64-opc.c: Likewise.
-2016-06-14 Graham Markall <graham.markall@embecosm.com>
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
- * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
- * arc-opc.c: Add flag classes, insert/extract functions, and operands to
- support the above instructions.
+ * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
+ ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
+ (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
+ (print_insn_arg) <OP_REG28>: Add handler.
+ (validate_insn_args) <OP_REG28>: Handle.
+ (print_mips16_insn_arg): Handle MIPS16 instructions that require
+ 32-bit encoding and 9-bit immediates.
+ (print_insn_mips16): Handle MIPS16 instructions that require
+ 32-bit encoding and MFC0/MTC0 operand decoding.
+ * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
+ <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
+ (RD_C0, WR_C0, E2, E2MT): New macros.
+ (mips16_opcodes): Add entries for MIPS16e2 instructions:
+ GP-relative "addiu" and its "addu" spelling, "andi", "cache",
+ "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
+ "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
+ "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
+ "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
+ instructions, "swl", "swr", "sync" and its "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
+ "xori", "dmt", "dvpe", "emt" and "evpe". Add split
+ regular/extended entries for original MIPS16 ISA revision
+ instructions whose extended forms are subdecoded in the MIPS16e2
+ ISA revision: "li", "sll" and "srl".
-2016-06-14 Graham Markall <graham.markall@embecosm.com>
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
- * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
- imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
- csma, cbba, zncv, and hofs.
- * arc-opc.c: Add flag classes, insert/extract functions, and operands to
- support the above instructions.
+ * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
+ reference in CP0 move operand decoding.
-2016-06-06 Graham Markall <graham.markall@embecosm.com>
+2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
- * arc-nps400-tbl.h: Add andab and orab instructions.
+ * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
+ type to hexadecimal.
+ (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
-2016-06-06 Graham Markall <graham.markall@embecosm.com>
+2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
- * arc-nps400-tbl.h: Add addl-like instructions.
+ * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
+ "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
+ "sync_rmb" and "sync_wmb" as aliases.
+ * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
-2016-06-06 Graham Markall <graham.markall@embecosm.com>
+2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
- * arc-nps400-tbl.h: Add mxb and imxb instructions.
+ * arc-dis.c (parse_option): Update quarkse_em option..
+ * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
+ QUARKSE1.
+ (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
-2016-06-06 Graham Markall <graham.markall@embecosm.com>
+2017-05-03 Kito Cheng <kito.cheng@gmail.com>
- * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
- instructions.
+ * riscv-dis.c (print_insn_args): Handle 'Co' operands.
-2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2017-05-01 Michael Clark <michaeljclark@mac.com>
- * s390-dis.c (option_use_insn_len_bits_p): New file scope
- variable.
- (init_disasm): Handle new command line option "insnlength".
- (print_s390_disassembler_options): Mention new option in help
- output.
- (print_insn_s390): Use the encoded insn length when dumping
- unknown instructions.
+ * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
+ register.
-2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
- * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
- to the address and set as symbol address for LDS/ STS immediate operands.
+ * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
+ and branches and not synthetic data instructions.
-2016-06-07 Alan Modra <amodra@gmail.com>
+2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
- * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
- cpu for "vle" to e500.
- * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
- (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
- (PPCNONE): Delete, substitute throughout.
- (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
- except for major opcode 4 and 31.
- (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
+ * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
-2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
- * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
- ARM_EXT_RAS in relevant entries.
+ * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
+ * arc-opc.c (insert_r13el): New function.
+ (R13_EL): Define.
+ * arc-tbl.h: Add new enter/leave variants.
-2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
- PR binutils/20196
- * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
- opcodes for E6500.
+ * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
-2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
- PR binutis/18386
- * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
- (indir_v_mode): New.
- Add comments for '&'.
- (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
- (putop): Handle '&'.
- (intel_operand_size): Handle indir_v_mode.
- (OP_E_register): Likewise.
- * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
- 64-bit indirect call/jmp for AMD64.
- * i386-tbl.h: Regenerated
+ * mips-dis.c (print_mips_disassembler_options): Add
+ `no-aliases'.
-2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
- * arc-dis.c (struct arc_operand_iterator): New structure.
- (find_format_from_table): All the old content from find_format,
- with some minor adjustments, and parameter renaming.
- (find_format_long_instructions): New function.
- (find_format): Rewritten.
- (arc_insn_length): Add LSB parameter.
- (extract_operand_value): New function.
- (operand_iterator_next): New function.
- (print_insn_arc): Use new functions to find opcode, and iterator
- over operands.
- * arc-opc.c (insert_nps_3bit_dst_short): New function.
- (extract_nps_3bit_dst_short): New function.
- (insert_nps_3bit_src2_short): New function.
- (extract_nps_3bit_src2_short): New function.
- (insert_nps_bitop1_size): New function.
- (extract_nps_bitop1_size): New function.
- (insert_nps_bitop2_size): New function.
- (extract_nps_bitop2_size): New function.
- (insert_nps_bitop_mod4_msb): New function.
- (extract_nps_bitop_mod4_msb): New function.
- (insert_nps_bitop_mod4_lsb): New function.
- (extract_nps_bitop_mod4_lsb): New function.
- (insert_nps_bitop_dst_pos3_pos4): New function.
- (extract_nps_bitop_dst_pos3_pos4): New function.
- (insert_nps_bitop_ins_ext): New function.
- (extract_nps_bitop_ins_ext): New function.
- (arc_operands): Add new operands.
- (arc_long_opcodes): New global array.
- (arc_num_long_opcodes): New global.
- * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
-
-2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
-
- * nds32-asm.h: Add extern "C".
- * sh-opc.h: Likewise.
-
-2016-06-01 Graham Markall <graham.markall@embecosm.com>
-
- * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
- 0,b,limm to the rflt instruction.
-
-2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
-
- * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
- constant.
-
-2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/20145
- * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
- CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
- CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
- CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
- CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
- * i386-init.h: Regenerated.
+ * mips16-opc.c (AL): New macro.
+ (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
+ of "ld" and "lw" as aliases.
-2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/20145
- * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
- CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
- CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
- Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
- CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
- CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
- CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
- Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
- CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
- CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
- CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
- for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
- CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
- CpuRegMask for AVX512.
- (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
- and CpuRegMask.
- (set_bitfield_from_cpu_flag_init): New function.
- (set_bitfield): Remove const on f. Call
- set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
- * i386-opc.h (CpuRegMMX): New.
- (CpuRegXMM): Likewise.
- (CpuRegYMM): Likewise.
- (CpuRegZMM): Likewise.
- (CpuRegMask): Likewise.
- (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
- and cpuregmask.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2017-04-24 Tamar Christina <tamar.christina@arm.com>
-2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/20154
- * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
- (opcode_modifiers): Add AMD64 and Intel64.
- (main): Properly verify CpuMax.
- * i386-opc.h (CpuAMD64): Removed.
- (CpuIntel64): Likewise.
- (CpuMax): Set to CpuNo64.
- (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
- (AMD64): New.
- (Intel64): Likewise.
- (i386_opcode_modifier): Add amd64 and intel64.
- (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
- on call and jmp.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/20154
- * i386-gen.c (main): Fail if CpuMax is incorrect.
- * i386-opc.h (CpuMax): Set to CpuIntel64.
- * i386-tbl.h: Regenerated.
+ * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
+ arguments.
-2016-05-27 Nick Clifton <nickc@redhat.com>
+2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
+ Alan Modra <amodra@gmail.com>
- PR target/20150
- * msp430-dis.c (msp430dis_read_two_bytes): New function.
- (msp430dis_opcode_unsigned): New function.
- (msp430dis_opcode_signed): New function.
- (msp430_singleoperand): Use the new opcode reading functions.
- Only disassenmble bytes if they were successfully read.
- (msp430_doubleoperand): Likewise.
- (msp430_branchinstr): Likewise.
- (msp430x_callx_instr): Likewise.
- (print_insn_msp430): Check that it is safe to read bytes before
- attempting disassembly. Use the new opcode reading functions.
+ * ppc-opc.c (ELEV): Define.
+ (vle_opcodes): Add se_rfgi and e_sc.
+ (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
+ for E200Z4.
-2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
+2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
- * ppc-opc.c (CY): New define. Document it.
- (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
+ * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
-2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
+2017-04-21 Nick Clifton <nickc@redhat.com>
- * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
- CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
- and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
- CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
- CPU_ANY_AVX_FLAGS.
- * i386-init.h: Regenerated.
+ PR binutils/21380
+ * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
+ LD3R and LD4R.
-2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
+2017-04-13 Alan Modra <amodra@gmail.com>
- PR gas/20141
- * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
- CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
- * i386-init.h: Regenerated.
+ * epiphany-desc.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * ip2k-desc.c: Regenerate.
+ * iq2000-desc.c: Regenerate.
+ * lm32-desc.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * mep-desc.c: Regenerate.
+ * mt-desc.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
-2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
+2017-04-11 Alan Modra <amodra@gmail.com>
- * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
- CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
- * i386-init.h: Regenerated.
+ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
+ PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
+ PPC_OPCODE_TMR for e6500.
+ * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
+ (PPCVEC3): Define as PPC_OPCODE_POWER9.
+ (PPCVSX2): Define as PPC_OPCODE_POWER8.
+ (PPCVSX3): Define as PPC_OPCODE_POWER9.
+ (PPCHTM): Define as PPC_OPCODE_POWER8.
+ (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
-2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+2017-04-10 Alan Modra <amodra@gmail.com>
- * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
- information.
- (print_insn_arc): Set insn_type information.
- * arc-opc.c (C_CC): Add F_CLASS_COND.
- * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
- (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
- (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
- (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
- (brne, brne_s, jeq_s, jne_s): Likewise.
+ * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
+ * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
+ (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
+ removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
-2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+2017-04-09 Pip Cet <pipcet@gmail.com>
- * arc-tbl.h (neg): New instruction variant.
+ * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
+ appropriate floating-point precision directly.
-2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
+2017-04-07 Alan Modra <amodra@gmail.com>
- * arc-dis.c (find_format, find_format, get_auxreg)
- (print_insn_arc): Changed.
- * arc-ext.h (INSERT_XOP): Likewise.
+ * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
+ lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
+ lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
+ lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
+ vector instructions with E6500 not PPCVEC2.
-2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+2017-04-06 Pip Cet <pipcet@gmail.com>
- * tic54x-dis.c (sprint_mmr): Adjust.
- * tic54x-opc.c: Likewise.
+ * Makefile.am: Add wasm32-dis.c.
+ * configure.ac: Add wasm32-dis.c to wasm32 target.
+ * disassemble.c: Add wasm32 disassembler code.
+ * wasm32-dis.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
-2016-05-19 Alan Modra <amodra@gmail.com>
+2017-04-05 Pedro Alves <palves@redhat.com>
- * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
+ * arc-dis.c (parse_option, parse_disassembler_options): Constify.
+ * arm-dis.c (parse_arm_disassembler_options): Constify.
+ * ppc-dis.c (powerpc_init_dialect): Constify local.
+ * vax-dis.c (parse_disassembler_options): Constify.
-2016-05-19 Alan Modra <amodra@gmail.com>
+2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
- * ppc-opc.c: Formatting.
- (NSISIGNOPT): Define.
- (powerpc_opcodes <subis>): Use NSISIGNOPT.
+ * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
+ RISCV_GP_SYMBOL.
-2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
+2017-03-30 Pip Cet <pipcet@gmail.com>
- * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
- replacing references to `micromips_ase' throughout.
- (_print_insn_mips): Don't use file-level microMIPS annotation to
- determine the disassembly mode with the symbol table.
+ * configure.ac: Add (empty) bfd_wasm32_arch target.
+ * configure: Regenerate
+ * po/opcodes.pot: Regenerate.
-2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
+2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
- * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
+ Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
+ OSA2015.
+ * opcodes/sparc-opc.c (asi_table): New ASIs.
-2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+2017-03-29 Alan Modra <amodra@gmail.com>
- * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
- mips64r6.
- * mips-opc.c (D34): New macro.
- (mips_builtin_opcodes): Define bposge32c for DSPr3.
+ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
+ "raw" option.
+ (lookup_powerpc): Don't special case -1 dialect. Handle
+ PPC_OPCODE_RAW.
+ (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
+ lookup_powerpc call, pass it on second.
-2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
+2017-03-27 Alan Modra <amodra@gmail.com>
- * i386-dis.c (prefix_table): Add RDPID instruction.
- * i386-gen.c (cpu_flag_init): Add RDPID flag.
- (cpu_flags): Add RDPID bitfield.
- * i386-opc.h (enum): Add RDPID element.
- (i386_cpu_flags): Add RDPID field.
- * i386-opc.tbl: Add RDPID instruction.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Regenerate.
+ PR 21303
+ * ppc-dis.c (struct ppc_mopt): Comment.
+ (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
-2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
-
- * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
- branch type of a symbol.
- (print_insn): Likewise.
-
-2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
-
- * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
- Mainline Security Extensions instructions.
- (thumb_opcodes): Add entries for narrow ARMv8-M Security
- Extensions instructions.
- (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
- instructions.
- (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
- special registers.
-
-2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
-
-2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
- (arcExtMap_genOpcode): Likewise.
- * arc-opc.c (arg_32bit_rc): Define new variable.
- (arg_32bit_u6): Likewise.
- (arg_32bit_limm): Likewise.
-
-2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-gen.c (VERIFIER): Define.
- * aarch64-opc.c (VERIFIER): Define.
- (verify_ldpsw): Use static linkage.
- * aarch64-opc.h (verify_ldpsw): Remove.
- * aarch64-tbl.h: Use VERIFIER for verifiers.
-
-2016-04-28 Nick Clifton <nickc@redhat.com>
-
- PR target/19722
- * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
- * aarch64-opc.c (verify_ldpsw): New function.
- * aarch64-opc.h (verify_ldpsw): New prototype.
- * aarch64-tbl.h: Add initialiser for verifier field.
- (LDPSW): Set verifier to verify_ldpsw.
-
-2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/19983
- PR binutils/19984
- * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
- smaller than address size.
-
-2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
-
- * alpha-dis.c: Regenerate.
- * crx-dis.c: Likewise.
- * disassemble.c: Likewise.
- * epiphany-opc.c: Likewise.
- * fr30-opc.c: Likewise.
- * frv-opc.c: Likewise.
- * ip2k-opc.c: Likewise.
- * iq2000-opc.c: Likewise.
- * lm32-opc.c: Likewise.
- * lm32-opinst.c: Likewise.
- * m32c-opc.c: Likewise.
- * m32r-opc.c: Likewise.
- * m32r-opinst.c: Likewise.
- * mep-opc.c: Likewise.
- * mt-opc.c: Likewise.
- * or1k-opc.c: Likewise.
- * or1k-opinst.c: Likewise.
- * tic80-opc.c: Likewise.
- * xc16x-opc.c: Likewise.
- * xstormy16-opc.c: Likewise.
-
-2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
- fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
- calcsd, and calcxd instructions.
- * arc-opc.c (insert_nps_bitop_size): Delete.
- (extract_nps_bitop_size): Delete.
- (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
- (extract_nps_qcmp_m3): Define.
- (extract_nps_qcmp_m2): Define.
- (extract_nps_qcmp_m1): Define.
- (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
- (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
- (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
- NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
- NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
- NPS_QCMP_M3.
-
-2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
-
-2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * Makefile.in: Regenerated with automake 1.11.6.
- * aclocal.m4: Likewise.
-
-2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
- instructions.
- * arc-opc.c (insert_nps_cmem_uimm16): New function.
- (extract_nps_cmem_uimm16): New function.
- (arc_operands): Add NPS_XLDST_UIMM16 operand.
-
-2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-dis.c (arc_insn_length): New function.
- (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
- (find_format): Change insnLen parameter to unsigned.
-
-2016-04-13 Nick Clifton <nickc@redhat.com>
-
- PR target/19937
- * v850-opc.c (v850_opcodes): Correct masks for long versions of
- the LD.B and LD.BU instructions.
-
-2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (find_format): Check for extension flags.
- (print_flags): New function.
- (print_insn_arc): Update for .extCondCode, .extCoreRegister and
- .extAuxRegister.
- * arc-ext.c (arcExtMap_coreRegName): Use
- LAST_EXTENSION_CORE_REGISTER.
- (arcExtMap_coreReadWrite): Likewise.
- (dump_ARC_extmap): Update printing.
- * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
- (arc_aux_regs): Add cpu field.
- * arc-regs.h: Add cpu field, lower case name aux registers.
-
-2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-tbl.h: Add rtsc, sleep with no arguments.
-
-2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
- Initialize.
- (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
- (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
- (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
- (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
- (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
- (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
- (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
- (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
- (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
- (arc_opcode arc_opcodes): Null terminate the array.
- (arc_num_opcodes): Remove.
- * arc-ext.h (INSERT_XOP): Define.
- (extInstruction_t): Likewise.
- (arcExtMap_instName): Delete.
- (arcExtMap_insn): New function.
- (arcExtMap_genOpcode): Likewise.
- * arc-ext.c (ExtInstruction): Remove.
- (create_map): Zero initialize instruction fields.
- (arcExtMap_instName): Remove.
- (arcExtMap_insn): New function.
- (dump_ARC_extmap): More info while debuging.
- (arcExtMap_genOpcode): New function.
- * arc-dis.c (find_format): New function.
- (print_insn_arc): Use find_format.
- (arc_get_disassembler): Enable dump_ARC_extmap only when
- debugging.
+2017-03-27 Rinat Zelig <rinat@mellanox.com>
-2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
+ * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
+ * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
+ F_NPS_M, F_NPS_CORE, F_NPS_ALL.
+ (insert_nps_misc_imm_offset): New function.
+ (extract_nps_misc imm_offset): New function.
+ (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
+ (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
- * mips-dis.c (print_mips16_insn_arg): Mask unused extended
- instruction bits out.
+2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+ * s390-mkopc.c (main): Remove vx2 check.
+ * s390-opc.txt: Remove vx2 instruction flags.
- * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
- * arc-opc.c (arc_flag_operands): Add new flags.
- (arc_flag_classes): Add new classes.
+2017-03-21 Rinat Zelig <rinat@mellanox.com>
-2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+ * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
+ * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
+ (insert_nps_imm_offset): New function.
+ (extract_nps_imm_offset): New function.
+ (insert_nps_imm_entry): New function.
+ (extract_nps_imm_entry): New function.
- * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
+2017-03-17 Alan Modra <amodra@gmail.com>
-2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
+ PR 21248
+ * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
+ mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
+ those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
- * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
- encode1, rflt, crc16, and crc32 instructions.
- * arc-opc.c (arc_flag_operands): Add F_NPS_R.
- (arc_flag_classes): Add C_NPS_R.
- (insert_nps_bitop_size_2b): New function.
- (extract_nps_bitop_size_2b): Likewise.
- (insert_nps_bitop_uimm8): Likewise.
- (extract_nps_bitop_uimm8): Likewise.
- (arc_operands): Add new operand entries.
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
-2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
+ * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
+ <c.andi>: Likewise.
+ <c.addiw> Likewise.
- * arc-regs.h: Add a new subclass field. Add double assist
- accumulator register values.
- * arc-tbl.h: Use DPA subclass to mark the double assist
- instructions. Use DPX/SPX subclas to mark the FPX instructions.
- * arc-opc.c (RSP): Define instead of SP.
- (arc_aux_regs): Add the subclass field.
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
-2016-04-05 Jiong Wang <jiong.wang@arm.com>
+ * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
- * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
+2017-03-13 Andrew Waterman <andrew@sifive.com>
-2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
+ * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
+ <srl> Likewise.
+ <srai> Likewise.
+ <sra> Likewise.
- * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
- NPS_R_SRC1.
+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
-2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
+ * i386-gen.c (opcode_modifiers): Replace S with Load.
+ * i386-opc.h (S): Removed.
+ (Load): New.
+ (i386_opcode_modifier): Replace s with load.
+ * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
+ and {evex}. Replace S with Load.
+ * i386-tbl.h: Regenerated.
- * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
- issues. No functional changes.
+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
-2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
+ * i386-opc.tbl: Use CpuCET on rdsspq.
+ * i386-tbl.h: Regenerated.
- * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
- (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
- (RTT): Remove duplicate.
- (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
- (PCT_CONFIG*): Remove.
- (D1L, D1H, D2H, D2L): Define.
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
+ <vsx>: Do not use PPC_OPCODE_VSX3;
+
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
+
+2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_0F1E_MOD_3): New enum.
+ (MOD_0F1E_PREFIX_1): Likewise.
+ (MOD_0F38F5_PREFIX_2): Likewise.
+ (MOD_0F38F6_PREFIX_0): Likewise.
+ (RM_0F1E_MOD_3_REG_7): Likewise.
+ (PREFIX_MOD_0_0F01_REG_5): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
+ (PREFIX_0F1E): Likewise.
+ (PREFIX_MOD_0_0FAE_REG_5): Likewise.
+ (PREFIX_0F38F5): Likewise.
+ (dis386_twobyte): Use PREFIX_0F1E.
+ (reg_table): Add REG_0F1E_MOD_3.
+ (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
+ PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
+ PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
+ (three_byte_table): Use PREFIX_0F38F5.
+ (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
+ Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
+ (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
+ RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
+ PREFIX_MOD_3_0F01_REG_5_RM_2.
+ * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
+ (cpu_flags): Add CpuCET.
+ * i386-opc.h (CpuCET): New enum.
+ (CpuUnused): Commented out.
+ (i386_cpu_flags): Add cpucet.
+ * i386-opc.tbl: Add Intel CET instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
-2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+2017-03-06 Alan Modra <amodra@gmail.com>
+
+ PR 21124
+ * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
+ (extract_raq, extract_ras, extract_rbx): New functions.
+ (powerpc_operands): Use opposite corresponding insert function.
+ (Q_MASK): Define.
+ (powerpc_opcodes): Apply Q_MASK to all quad insns with even
+ register restriction.
+
+2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
+
+ * disassemble.c Include "safe-ctype.h".
+ (disassemble_init_for_target): Handle s390 init.
+ (remove_whitespace_and_extra_commas): New function.
+ (disassembler_options_cmp): Likewise.
+ * arm-dis.c: Include "libiberty.h".
+ (NUM_ELEM): Delete.
+ (regnames): Use long disassembler style names.
+ Add force-thumb and no-force-thumb options.
+ (NUM_ARM_REGNAMES): Rename from this...
+ (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
+ (get_arm_regname_num_options): Delete.
+ (set_arm_regname_option): Likewise.
+ (get_arm_regnames): Likewise.
+ (parse_disassembler_options): Likewise.
+ (parse_arm_disassembler_option): Rename from this...
+ (parse_arm_disassembler_options): ...to this. Make static.
+ Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
+ (print_insn): Use parse_arm_disassembler_options.
+ (disassembler_options_arm): New function.
+ (print_arm_disassembler_options): Handle updated regnames.
+ * ppc-dis.c: Include "libiberty.h".
+ (ppc_opts): Add "32" and "64" entries.
+ (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
+ (powerpc_init_dialect): Add break to switch statement.
+ Use new FOR_EACH_DISASSEMBLER_OPTION macro.
+ (disassembler_options_powerpc): New function.
+ (print_ppc_disassembler_options): Use ARRAY_SIZE.
+ Remove printing of "32" and "64".
+ * s390-dis.c: Include "libiberty.h".
+ (init_flag): Remove unneeded variable.
+ (struct s390_options_t): New structure type.
+ (options): New structure.
+ (init_disasm): Rename from this...
+ (disassemble_init_s390): ...to this. Add initializations for
+ current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
+ (print_insn_s390): Delete call to init_disasm.
+ (disassembler_options_s390): New function.
+ (print_s390_disassembler_options): Print using information from
+ struct 'options'.
+ * po/opcodes.pot: Regenerate.
- * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
+2017-02-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PCMPESTR_Fixup): New.
+ (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
+ (prefix_table): Use PCMPESTR_Fixup.
+ (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
+ PCMPESTR_Fixup.
+ (vex_w_table): Delete VPCMPESTR{I,M} entries.
+ * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
+ Split 64-bit and non-64-bit variants.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
+ (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
+ (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
+ (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
+ (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
+ (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
+ (OP_SVE_V_HSD): New macros.
+ (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
+ (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
+ (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
+ (aarch64_opcode_table): Add new SVE instructions.
+ (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
+ for rotation operands. Add new SVE operands.
+ * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
+ (ins_sve_quad_index): Likewise.
+ (ins_imm_rotate): Split into...
+ (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
+ * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
+ (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
+ functions.
+ (aarch64_ins_sve_addr_ri_s4): New function.
+ (aarch64_ins_sve_quad_index): Likewise.
+ (do_misc_encoding): Handle "MOV Zn.Q, Qm".
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
+ (ext_sve_quad_index): Likewise.
+ (ext_imm_rotate): Split into...
+ (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
+ * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
+ (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
+ functions.
+ (aarch64_ext_sve_addr_ri_s4): New function.
+ (aarch64_ext_sve_quad_index): Likewise.
+ (aarch64_ext_sve_index): Allow quad indices.
+ (do_misc_decoding): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
+ aarch64_field_kinds.
+ (OPD_F_OD_MASK): Widen by one bit.
+ (OPD_F_NO_ZR): Bump accordingly.
+ (get_operand_field_width): New function.
+ * aarch64-opc.c (fields): Add new SVE fields.
+ (operand_general_constraint_met_p): Handle new SVE operands.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc-2.c: Regenerate.
-2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
- * arc-tbl.h (invld07): Remove.
- * arc-ext-tbl.h: New file.
- * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
- * arc-opc.c (arc_opcodes): Add ext-tbl include.
+ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
+ (aarch64_feature_compnum): ...this.
+ (SIMD_V8_3): Replace with...
+ (COMPNUM): ...this.
+ (CNUM_INSN): New macro.
+ (aarch64_opcode_table): Use it for the complex number instructions.
-2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
+2017-02-24 Jan Beulich <jbeulich@suse.com>
- Fix -Wstack-usage warnings.
- * aarch64-dis.c (print_operands): Substitute size.
- * aarch64-opc.c (print_register_offset_address): Substitute tblen.
+ * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
-2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
- * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
- to get a proper diagnostic when an invalid ASR register is used.
+ Add support for associating SPARC ASIs with an architecture level.
+ * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
+ * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
+ decoding of SPARC ASIs.
-2016-03-22 Nick Clifton <nickc@redhat.com>
+2017-02-23 Jan Beulich <jbeulich@suse.com>
- * configure: Regenerate.
+ * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
+ 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
-2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-02-21 Jan Beulich <jbeulich@suse.com>
- * arc-nps400-tbl.h: New file.
- * arc-opc.c: Add top level comment.
- (insert_nps_3bit_dst): New function.
- (extract_nps_3bit_dst): New function.
- (insert_nps_3bit_src2): New function.
- (extract_nps_3bit_src2): New function.
- (insert_nps_bitop_size): New function.
- (extract_nps_bitop_size): New function.
- (arc_flag_operands): Add nps400 entries.
- (arc_flag_classes): Add nps400 entries.
- (arc_operands): Add nps400 entries.
- (arc_opcodes): Add nps400 include.
+ * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
+ 1 (instead of to itself). Correct typo.
-2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-02-14 Andrew Waterman <andrew@sifive.com>
- * arc-opc.c (arc_flag_classes): Convert all flag classes to use
- the new class enum values.
+ * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+ pseudoinstructions.
-2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
- * arc-dis.c (print_insn_arc): Handle nps400.
+ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
+ (aarch64_sys_reg_supported_p): Handle them.
-2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
- * arc-opc.c (BASE): Delete.
+ * arc-opc.c (UIMM6_20R): Define.
+ (SIMM12_20): Use above.
+ (SIMM12_20R): Define.
+ (SIMM3_5_S): Use above.
+ (UIMM7_A32_11R_S): Define.
+ (UIMM7_9_S): Use above.
+ (UIMM3_13R_S): Define.
+ (SIMM11_A32_7_S): Use above.
+ (SIMM9_8R): Define.
+ (UIMM10_A32_8_S): Use above.
+ (UIMM8_8R_S): Define.
+ (W6): Use above.
+ (arc_relax_opcodes): Use all above defines.
-2016-03-18 Nick Clifton <nickc@redhat.com>
+2017-02-15 Vineet Gupta <vgupta@synopsys.com>
- PR target/19721
- * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
- of MOV insn that aliases an ORR insn.
+ * arc-regs.h: Distinguish some of the registers different on
+ ARC700 and HS38 cpus.
-2016-03-16 Jiong Wang <jiong.wang@arm.com>
+2017-02-14 Alan Modra <amodra@gmail.com>
- * arm-dis.c (neon_opcodes): Support new FP16 instructions.
+ PR 21118
+ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
+ with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
-2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+2017-02-11 Stafford Horne <shorne@gmail.com>
+ Alan Modra <amodra@gmail.com>
- * mcore-opc.h: Add const qualifiers.
- * microblaze-opc.h (struct op_code_struct): Likewise.
- * sh-opc.h: Likewise.
- * tic4x-dis.c (tic4x_print_indirect): Likewise.
- (tic4x_print_op): Likewise.
+ * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
+ Use insn_bytes_value and insn_int_value directly instead. Don't
+ free allocated memory until function exit.
-2016-03-02 Alan Modra <amodra@gmail.com>
+2017-02-10 Nicholas Piggin <npiggin@gmail.com>
- * or1k-desc.h: Regenerate.
- * fr30-ibld.c: Regenerate.
- * rl78-decode.c: Regenerate.
+ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
-2016-03-01 Nick Clifton <nickc@redhat.com>
+2017-02-03 Nick Clifton <nickc@redhat.com>
- PR target/19747
- * rl78-dis.c (print_insn_rl78_common): Fix typo.
+ PR 21096
+ * aarch64-opc.c (print_register_list): Ensure that the register
+ list index will fir into the tb buffer.
+ (print_register_offset_address): Likewise.
+ * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
-2016-02-24 Renlin Li <renlin.li@arm.com>
+2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
- * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
- (print_insn_coprocessor): Support fp16 instructions.
+ PR 21056
+ * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
+ instructions when the previous fetch packet ends with a 32-bit
+ instruction.
-2016-02-24 Renlin Li <renlin.li@arm.com>
+2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
- * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
- vminnm, vrint(mpna).
+ * pru-opc.c: Remove vague reference to a future GDB port.
-2016-02-24 Renlin Li <renlin.li@arm.com>
+2017-01-20 Nick Clifton <nickc@redhat.com>
- * arm-dis.c (print_insn_coprocessor): Check co-processor number for
- cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
+ * po/ga.po: Updated Irish translation.
-2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
+2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
- * i386-dis.c (print_insn): Parenthesize expression to prevent
- truncated addresses.
- (OP_J): Likewise.
+ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
-2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
- Janek van Oirschot <jvanoirs@synopsys.com>
+2017-01-13 Yao Qi <yao.qi@linaro.org>
- * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
- variable.
+ * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
+ if FETCH_DATA returns 0.
+ (m68k_scan_mask): Likewise.
+ (print_insn_m68k): Update code to handle -1 return value.
-2016-02-04 Nick Clifton <nickc@redhat.com>
+2017-01-13 Yao Qi <yao.qi@linaro.org>
- PR target/19561
- * msp430-dis.c (print_insn_msp430): Add a special case for
- decoding an RRC instruction with the ZC bit set in the extension
- word.
+ * m68k-dis.c (enum print_insn_arg_error): New.
+ (NEXTBYTE): Replace -3 with
+ PRINT_INSN_ARG_MEMORY_ERROR.
+ (NEXTULONG): Likewise.
+ (NEXTSINGLE): Likewise.
+ (NEXTDOUBLE): Likewise.
+ (NEXTDOUBLE): Likewise.
+ (NEXTPACKED): Likewise.
+ (FETCH_ARG): Likewise.
+ (FETCH_DATA): Update comments.
+ (print_insn_arg): Update comments. Replace magic numbers with
+ enum.
+ (match_insn_m68k): Likewise.
-2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
- * cgen-ibld.in (insert_normal): Rework calculation of shift.
- * epiphany-ibld.c: Regenerate.
- * fr30-ibld.c: Regenerate.
- * frv-ibld.c: Regenerate.
- * ip2k-ibld.c: Regenerate.
- * iq2000-ibld.c: Regenerate.
- * lm32-ibld.c: Regenerate.
- * m32c-ibld.c: Regenerate.
- * m32r-ibld.c: Regenerate.
- * mep-ibld.c: Regenerate.
- * mt-ibld.c: Regenerate.
- * or1k-ibld.c: Regenerate.
- * xc16x-ibld.c: Regenerate.
- * xstormy16-ibld.c: Regenerate.
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
+ CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
+ * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
+ (i386_cpu_flags): Add cpuavx512_vpopcntdq.
+ * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
-2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+2017-01-12 Yao Qi <yao.qi@linaro.org>
- * epiphany-dis.c: Regenerated from latest cpu files.
+ * msp430-dis.c (msp430_singleoperand): Return -1 if
+ msp430dis_opcode_signed returns false.
+ (msp430_doubleoperand): Likewise.
+ (msp430_branchinstr): Return -1 if
+ msp430dis_opcode_unsigned returns false.
+ (msp430x_calla_instr): Likewise.
+ (print_insn_msp430): Likewise.
-2016-02-01 Michael McConville <mmcco@mykolab.com>
+2017-01-05 Nick Clifton <nickc@redhat.com>
- * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
- test bit.
+ PR 20946
+ * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
+ could not be matched.
+ (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
+ NULL.
-2016-01-25 Renlin Li <renlin.li@arm.com>
+2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
- * arm-dis.c (mapping_symbol_for_insn): New function.
- (find_ifthen_state): Call mapping_symbol_for_insn().
+ * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
+ (aarch64_opcode_table): Use RCPC_INSN.
-2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
+2017-01-03 Kito Cheng <kito.cheng@gmail.com>
- * aarch64-opc.c (operand_general_constraint_met_p): Check validity
- of MSR UAO immediate operand.
+ * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
+ extension.
+ * riscv-opcodes/all-opcodes: Likewise.
-2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
+2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
- * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
- instruction support.
+ * riscv-dis.c (print_insn_args): Add fall through comment.
-2016-01-17 Alan Modra <amodra@gmail.com>
+2017-01-03 Nick Clifton <nickc@redhat.com>
+ * po/sr.po: New Serbian translation.
+ * configure.ac (ALL_LINGUAS): Add sr.
* configure: Regenerate.
-2016-01-14 Nick Clifton <nickc@redhat.com>
-
- * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
- instructions that can support stack pointer operations.
- * rl78-decode.c: Regenerate.
- * rl78-dis.c: Fix display of stack pointer in MOVW based
- instructions.
-
-2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
- testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
- erxtatus_el1 and erxaddr_el1.
-
-2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
-
- * arm-dis.c (arm_opcodes): Add "esb".
- (thumb_opcodes): Likewise.
-
-2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-opc.c <xscmpnedp>: Delete.
- <xvcmpnedp>: Likewise.
- <xvcmpnedp.>: Likewise.
- <xvcmpnesp>: Likewise.
- <xvcmpnesp.>: Likewise.
-
-2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
-
- PR gas/13050
- * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
- addition to ISA_A.
+2017-01-02 Alan Modra <amodra@gmail.com>
+
+ * epiphany-desc.h: Regenerate.
+ * epiphany-opc.h: Regenerate.
+ * fr30-desc.h: Regenerate.
+ * fr30-opc.h: Regenerate.
+ * frv-desc.h: Regenerate.
+ * frv-opc.h: Regenerate.
+ * ip2k-desc.h: Regenerate.
+ * ip2k-opc.h: Regenerate.
+ * iq2000-desc.h: Regenerate.
+ * iq2000-opc.h: Regenerate.
+ * lm32-desc.h: Regenerate.
+ * lm32-opc.h: Regenerate.
+ * m32c-desc.h: Regenerate.
+ * m32c-opc.h: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-opc.h: Regenerate.
+ * mep-desc.h: Regenerate.
+ * mep-opc.h: Regenerate.
+ * mt-desc.h: Regenerate.
+ * mt-opc.h: Regenerate.
+ * or1k-desc.h: Regenerate.
+ * or1k-opc.h: Regenerate.
+ * xc16x-desc.h: Regenerate.
+ * xc16x-opc.h: Regenerate.
+ * xstormy16-desc.h: Regenerate.
+ * xstormy16-opc.h: Regenerate.
-201
6-01-01 Alan Modra <amodra@gmail.com>
+201
7-01-02 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2015
+For older changes see ChangeLog-2016
\f
-Copyright (C) 2016 Free Software Foundation, Inc.
+Copyright (C) 2017 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff