+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_shorthands): New.
+ (opcode_modifiers): Replace Reg<N> with just Reg.
+ (set_bitfield_from_cpu_flag_init): Rename to
+ set_bitfield_from_shorthand. Drop value parameter. Process
+ operand_type_shorthands.
+ (set_bitfield): Adjust call accordingly.
+ * i386-opc.h (enum of operand types): Replace Reg<N> with just
+ Reg.
+ (union i386_operand_type): Replace reg<N> with just reg.
+ * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
+ vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
+ separate register and memory forms.
+ * i386-reg.tbl (al): Drop Byte.
+ (ax): Drop Word.
+ (eax): Drop Dword.
+ (rax): Drop Qword.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * disassemble.c (disassemble_init_for_target): Don't put PRU
+ between powerpc and rs6000 cases.
+
+2017-12-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
+ movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
+ sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
+ stos, sub, test, xor): Drop CheckRegSize from variants not
+ allowing for two (or more) register operands.
+ * i386-tbl.h: Re-generate.
+
+2017-12-13 Jim Wilson <jimw@sifive.com>
+
+ PR 22599
+ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
+
+2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * disassemble.c: Enable disassembler_needs_relocs for PRU.
+
+2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
+ Renlin Li <renlin.li@arm.com>
+
+ * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
+ (get_sym_code_type): Here.
+
+2017-12-03 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (extract_li20): Rewrite.
+
+2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
+ (operand_value_powerpc): Update return and argument type.
+ <value, top>: Update type.
+ (skip_optional_operands): Update argument type.
+ (lookup_powerpc): Likewise.
+ (lookup_vle): Likewise.
+ <table_opcd, table_mask, insn2>: Update type.
+ (lookup_spe2): Update argument type.
+ <table_opcd, table_mask, insn2>: Update type.
+ (print_insn_powerpc) <insn, value>: Update type.
+ Use PPC_INT_FMT for printing instructions and operands.
+ * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
+ insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
+ insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
+ extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
+ extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
+ insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
+ extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
+ insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
+ extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
+ insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
+ extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
+ insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
+ extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
+ insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
+ extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
+ insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
+ extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
+ insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
+ extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
+ extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
+ extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
+ insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
+ extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
+ insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
+ extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
+ extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
+ (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
+ BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
+ DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
+ SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
+ VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
+ VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
+ VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
+ XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
+ XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
+ XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
+ XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
+ New.
+ (output_cpu_flags): Update active_cpu_flags.
+ (process_i386_opcode_modifier): Update active_isstring.
+ (output_operand_type): Rename "macro" parameter to "stage",
+ changing its type.
+ (process_i386_operand_type): Likewise. Track presence of
+ BaseIndex and emit DispN accordingly.
+ (output_i386_opcode, process_i386_registers,
+ process_i386_initializers): Adjust calls to
+ process_i386_operand_type() for its changed parameter type.
+ * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
+ all insns operands having BaseIndex set.
+ * i386-tbl.h: Re-generate.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
+ entry.
+ (operand_types): Remove Vec_Disp8 entry.
+ * i386-opc.h (Vec_Disp8): Delete.
+ (union i386_operand_type): Remove vec_disp8.
+ (i386-opc.tbl): Remove Vec_Disp8.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2017-11-29 Stefan Stroe <stroestefan@gmail.com>
+
+ * po/Make-in (datadir): Define as @datadir@.
+ (localedir): Define as @localedir@.
+ (gnulocaledir, gettextsrcdir): Use @datarootdir@.
+
+2017-11-27 Nick Clifton <nickc@redhat.com>
+
+ * po/zh_CN.po: Updated simplified Chinese translation.
+
+2017-11-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
+ "df" groups.
+
+2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
+ * i386-tbl.h: Regenerate.
+
+2017-11-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
+ the 16-bit addressing case.
+
+2017-11-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
+ (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
+ * i386-opc.tbl (ud1, ud2b): Add operands.
+ (ud0): New.
+ * i386-tbl.h: Re-generate.
+
+2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
+ * i386-tbl.h: Regenerate.
+
+2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
+ * i386-tbl.h: Regenerate.
+
+2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
+
+ *arc-opc (insert_rhv2): Check h-regs range.
+
+2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
+ * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
+
+2017-11-16 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
+ and AARCH64_FEATURE_F16.
+
+2017-11-16 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
+ (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
+ (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
+ (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
+ (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
+ (ldapur, ldapursw, stlur): New.
+ * aarch64-dis-2.c: Regenerate.
+
2017-11-16 Jan Beulich <jbeulich@suse.com>
(get_valid_dis386): Never flag bad opcode when