x86: replace Reg8, Reg16, Reg32, and Reg64

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dbc29fafb4a790a1350fa2495168814d09afd4f0..19e27af1d39eb18cbe89c61be20aa587e63c7dc4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,37 @@
+2017-12-18  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_type_shorthands): New.
+       (opcode_modifiers): Replace Reg<N> with just Reg.
+       (set_bitfield_from_cpu_flag_init): Rename to
+       set_bitfield_from_shorthand. Drop value parameter. Process
+       operand_type_shorthands.
+       (set_bitfield): Adjust call accordingly.
+       * i386-opc.h (enum of operand types): Replace Reg<N> with just
+       Reg.
+       (union i386_operand_type): Replace reg<N> with just reg.
+       * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
+       vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
+       separate register and memory forms.
+       * i386-reg.tbl (al): Drop Byte.
+       (ax): Drop Word.
+       (eax): Drop Dword.
+       (rax): Drop Qword.
+       * i386-init.h, i386-tbl.h: Re-generate.
+
+2017-12-15  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+       * disassemble.c (disassemble_init_for_target): Don't put PRU
+       between powerpc and rs6000 cases.
+
+2017-12-15  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
+       movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
+       sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
+       stos, sub, test, xor): Drop CheckRegSize from variants not
+       allowing for two (or more) register operands.
+       * i386-tbl.h: Re-generate.
+
 2017-12-13  Jim Wilson  <jimw@sifive.com>
 
        PR 22599