ix86: Disable AVX512F when disabling AVX2

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 23a0d7fd291029737bd554d829363ca32e776bd0..204c008ab4cc834b234c07cc10a1cf40c3d33e4a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,72 @@
+2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/24359
+       * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
+       CPU_ANY_AVX2_FLAGS.
+       * i386-init.h: Regenerated.
+
+2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/24348
+       * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
+       vmovdqu16, vmovdqu32 and vmovdqu64.
+       * i386-tbl.h: Regenerated.
+
+2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
+       from vstrszb, vstrszh, and vstrszf.
+
+2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * s390-opc.txt: Add instruction descriptions.
+
+2019-02-08  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
+       <bne>: Likewise.
+
+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+       * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
+
+2019-02-07  Tamar Christina  <tamar.christina@arm.com>
+
+       PR binutils/23212
+       * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
+       * aarch64-opc.c (verify_elem_sd): New.
+       (fields): Add FLD_sz entr.
+       * aarch64-tbl.h (_SIMD_INSN): New.
+       (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
+       fmulx scalar and vector by element isns.
+
+2019-02-07  Nick Clifton  <nickc@redhat.com>
+
+       * po/sv.po: Updated Swedish translation.
+
+2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * s390-mkopc.c (main): Accept arch13 as cpu string.
+       * s390-opc.c: Add new instruction formats and instruction opcode
+       masks.
+       * s390-opc.txt: Add new arch13 instructions.
+
+2019-01-25  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-tbl.h (QL_LDST_AT): Update macro.
+       (aarch64_opcode): Change encoding for stg, stzg
+       st2g and st2zg.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2019-01-25  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Likewise.
+       * aarch64-opc-2.c: Likewise.
+       * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
+
 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>