+2019-05-01 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_TME_UIMM16.
+ (aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (QL_IMM_NIL): New.
+ (TME): New.
+ (_TME_INSN): New.
+ (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
+
+2019-04-29 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
+
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.h: Add extern "C" bracketing to help
+ users who wish to use this interface in c++ code.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.c (bm_decode): Handle bit map operations with the
+ "reserved0" mode.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
+ specifier. Add entries for VLDR and VSTR of system registers.
+ (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
+ coprocessor instructions on Armv8.1-M Mainline targets. Add handling
+ of %J and %K format specifier.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
+ Add new entries for VSCCLRM instruction.
+ (print_insn_coprocessor): Handle new %C format control code.
+
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (enum isa): New enum.