+2017-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
+ (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
+ * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
+ vpcmpw): Move up.
+ (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
+ vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
+ vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
+ vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
+ vpcmpnltuw): New.
+ * i386-tbl.h: Re-generate.
+
+2017-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
+ smov, ssca, stos, ssto, xlat): Drop Disp*.
+ * i386-tbl.h: Re-generate.
+
+2017-11-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
+ xsaveopt64): Add No_qSuf.
+ * i386-tbl.h: Re-generate.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
+ dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
+ cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
+ sder32_el2, vncr_el2.
+ (aarch64_sys_reg_supported_p): Likewise.
+ (aarch64_pstatefields): Add dit register.
+ (aarch64_pstatefield_supported_p): Likewise.
+ (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
+ vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
+ vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
+ rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
+ rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
+ ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
+ rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
+ (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
+ (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
+ (QL_STLW, QL_STLX): New.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.h (ins_addr_offset): New.
+ * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
+ (aarch64_ins_addr_offset): New.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_addr_offset): New.
+ * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
+ (aarch64_ext_addr_offset): New.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ * aarch64-opc.c (fields): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
+ (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+ AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
+ * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
+ * aarch64-tbl.h
+ (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h