aarch64: Update LS64 feature with system register

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7dce84a120bdf59fc955bf70b94658cb510cc735..34b2b62d51facbc6a8efbfc36fd04d0fb342711b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,133 @@
+2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add ACCDATA_EL1 system register
+
+2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
+       print.
+       * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
+       Rt_ls64 operands.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (PAC): Handle for PAC feature.
+       (PAC_INSN): New PAC instruction.
+       (struct aarch64_opcode):  Move PAC instructions from V8_3_INSN to
+       PAC_INSN.
+
+2020-11-04  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
+       ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
+
+2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
+       (LS64): Handler with +ls64 feature flags.
+       (_LS64_INSN): New instruction group macro.
+       (struct aarch64_opcode): Add LS64 instructions.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
+       * aarch64-tbl.h (CSRE): New CSRE feature handler.
+       (_CSRE_INSN): New CSRE instruction type.
+       (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
+       and operand description.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
+
+       * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
+
+2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
+
+       * csky-dis.c (csky_output_operand): Add handler for
+       OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
+       * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
+       (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
+       some instructions for VDSPV1.
+
+2020-10-26  Lili Cui  <lili.cui@intel.com>
+
+       * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. 
+
+2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
+       * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
+       ins_barrier_dsb_nx.
+       * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
+       * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
+       ext_barrier_dsb_nx.
+       * aarch64-opc.c (aarch64_print_operand): New options table
+       aarch64_barrier_dsb_nxs_options.
+       * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
+       * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
+       Armv8.7-a instruction.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * po/es.po: Remove the duplicated entry.
+
+2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
+
+       * po/es.po: Fix printf format.
+
+2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
+
+       * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
+       * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
+       CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
+       Add CPU_ZNVER3_FLAGS.
+       (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
+       * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
+       * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
+       rmpupdate, rmpadjust.
+       * i386-init.h: Re-generated.
+       * i386-tbl.h: Re-generated.
+
+2020-10-16  Lili Cui  <lili.cui@intel.com>
+
+       * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
+       and move it from cpu_flags to opcode_modifiers.
+       Use VexW0 and VexVVVV in the AVX-VNNI instructions.
+       * i386-gen.c: Likewise.
+       * i386-opc.h: Likewise.
+       * i386-opc.h: Likewise.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (ARMV8_7): New macro.
+
 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
            Lili Cui  <lili.cui@intel.com>
 
@@ -96,6 +226,14 @@
        Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
        * i386-tbl.h: Regenerated.
 
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add BRBE system registers.
+
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: New CSRE system registers defined.
+
 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 
        * cgen-asm.c: Fix spelling mistakes.