+start-sanitize-sky
+Thu Feb 19 02:11:39 1998 Doug Evans <devans@charmed.cygnus.com>
+
+ * dvp-opc.c (dma_operands): Rewrite.
+ (dma_operand_{count,addr}): New globals.
+ (dma_opcodes): Rewrite. Add "dmaend" with no operands.
+ (insert_dma_addr): Insert value into insn.
+ (extract_dma_addr): Extract value from insn.
+
+Wed Feb 18 15:46:46 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * dvp-dis.c (print_vu): Handle loi insns.
+ (print_insn): Likewise.
+ * dvp-opc.c (vu_lower_opcodes): Add "loi".
+ (vu_operands): Make LDEST1 a FAKE operand.
+ (parse_dest1): Allow elided argument.
+ (print_dest1): Don't print the argument.
+
+Tue Feb 17 18:48:25 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * dvp-opc.c (parse_vfreg): Dest spec is optional.
+ (print_vfreg): Don't print dest spec.
+ (parse_accdest): Dest spec is optional.
+ (print_accdest): Don't print dest spec.
+
+end-sanitize-sky
+Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * Makefile.am (CGENFILES): Update.
+ * Makefile.in: Regenerate.
+ * cgen-asm.in (insert_normal): Result is error message now.
+ Validate value to be inserted.
+ (insert_insn_normal): Result is error message now.
+ (@arch@_cgen_assemble_insn): Update.
+ * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max
+ arguments. Don't perform validation here.
+ * m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate.
+
+Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * cgen-opc.in (@arch@_cgen_get_insn_operands): Handle empty
+ operand instance list.
+ * m32r-opc.c: Regenerate.
+
+Fri Feb 13 14:53:02 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.am (AUTOMAKE_OPTIONS): Define.
+ * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e.
+
+Fri Feb 13 10:21:09 1998 Mark Alexander <marka@cygnus.com>
+
+ * m10300-dis.c (print_insn_mn10300): Recognize break instruction.
+
+Fri Feb 13 13:12:14 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Get the version number from BFD.
+ * configure: Rebuild.
+
+ From H.J. Lu <hjl@gnu.org>:
+ * Makefile.am (libopcodes_la_LDFLAGS): Define.
+ * Makefile.in: Rebuild.
+
+Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
+
+Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * cgen-opc.in (@arch@_cgen_lookup_insn): New argument alias_p.
+ Ignore ALIAS insns if asked to.
+ (@arch@_cgen_get_insn_operands): Pass 0 for alias_p, NULL for insn.
+ * m32r-opc.c: Regenerate.
+
+start-sanitize-sky
+ * dvp.opc.c: Nicely format opcode tables.
+ (vu_operands): New element UFLAGS.
+ (parse_uflags,print_uflags): New functions.
+ (vu_upper_opcodes): Add UFLAGS to all insns.
+
+end-sanitize-sky
+Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ Fix rac to accept only a0:
+ * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes):
+ Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1.
+ Introduce OPERAND_GPR.
+ * d10v-dis.c (print_operand): Likewise.
+
+Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-opc.in: New file.
+ * cgen.sh: Translate @ARCH@. Cat cgen-opc.in into @arch@-opc.c.
+ * Makefile.am (CGENFILES): Add cgen-opc.in.
+ * Makefile.in: Regenerate.
+
+ * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain.
+ (cgen_hw_lookup): Make result const.
+
+ * cgen-dis.in (*): Use PTR instead of void *.
+ (print_insn): Delete unused vars `i', `syntax'.
+
+ * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
+
+start-sanitize-sky
+Tue Feb 10 14:56:24 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * dvp-opc.c (*): pke,gpuif renamed to vif,gif.
+ (vif_opcodes): Update renamed insns.
+ * dvp-dis.c (*): Likewise.
+
+end-sanitize-sky
+Sat Feb 7 15:30:27 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure, aclocal.m4: Rebuild with new libtool.
+
+start-sanitize-d30v
+Thu Feb 5 17:56:10 1998 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (repeat{,i} instructions): Repeat/repeati
+ instructions use a PC relative branch, not absolute.
+
+end-sanitize-d30v
+Wed Feb 4 19:17:37 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Set libtool_enable_shared rather than
+ libtool_shared. Remove diversion hack.
+ * configure, Makefile.in, aclocal.m4: Rebuild with new libtool.
+
+Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-opc.c (cgen_set_cpu): Initialize hardware table.
+ * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
+
+Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU>
+
+ * tic30-dis.c: New file.
+ * disassemble.c (disassembler): Add bfd_arch_tic30 case.
+ * configure.in: Handle bfd_tic30_arch.
+ * Makefile.am: Rebuild dependencies.
+ (CFILES): Add tic30-dis.c
+ (ALL_MACHINES): Add tic30-dis.lo.
+ * configure, Makefile.in: Rebuild.
+
+start-sanitize-m32rx
+Mon Feb 2 11:04:08 1998 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-opc.c, m32r-opc.h, m32r-asm.c m32r-dis.c: Newly generated
+ versions after updates to m32r.cpu to remove mulwhi-a, mulwlo-a,
+ macwhi-a and macwlo-a instructions.
+
+end-sanitize-m32rx
+start-sanitize-sky
+Fri Jan 30 17:39:21 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * dvp-opc.c, fixed encoding of a bunch of instructions to
+ be consistent with the asmvu assembler (and inconsistent
+ with the specification).
+
+Thu Jan 29 18:14:56 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * dvp-opc.c, fixed order of pkemscal/pkemscalf instructions
+ in the opcode table. The pkemscalf instruction must come first.
+
+Thu Jan 29 16:47:24 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * dvp-opc.c, MAXIi should be VUOP6(0x1d) instead of 0x2d.
+
+end-sanitize-sky
+Thu Jan 29 13:02:56 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * m32r-opc.h (HAVE_CPU_M32R): Define.
+
+start-sanitize-sky
+Wed Jan 28 13:46:19 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * dvp-dis.c, dvp-opc.c: New files.
+ * configure.in: Compile them if bfd_dvp_arch, as well as mips.
+ * configure: Regenerate.
+ * Makefile.am (ALL_MACHINES): Add dvp-{dis,opc}.lo.
+ (dvp-dis.lo,dvp-opc.lo): Add rules for.
+ (mips-dis.lo): Compile with @archdefs@.
+ * Makefile.in: Regenerate.
+ * disassemble.c: Define ARCH_mips ifdef ARCH_dvp.
+ * mips-dis.c (print_insn_little_mips): Check for DVP insns.
+
+end-sanitize-sky
+Wed Jan 28 09:55:03 1998 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (insertion routines): If both alignment and size is
+ wrong then report this.
+
+Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-dis.c (_print_insn_mips): Set target_processor as appropriate.
+ Only recognize instructions for the current target_processor.
+
+Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com>
+
+ * d10v-dis.c (PC_MASK): Correct value.
+ (print_operand): If there's a reloc, don't calculate the
+ address because they could be in different sections.
+
+start-sanitize-cygnus
+Thu Jan 22 16:10:32 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.sh: Rewrite to be like simulator's version.
+ * Makefile.am (cgen): Update call to cgen.sh.
+ * Makefile.in: Regenerate
+
+end-sanitize-cygnus
+Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu"
+ instruction after the 4650's "mul" instruction; nobody's using the
+ 4010 these days. If object files someday indicate which processor
+ variant they're intended for, we can do a better job at this.
+
+start-sanitize-r5900
+Tue Jan 13 09:21:56 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (c.lt.s): Add r5900 variant.
+ (c.le.s): Likewise.
+
+end-sanitize-r5900
+Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MNEMONIC.
+ (cgen_parse_keyword): Rewrite.
+ * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MASK_BITSIZE.
+ * cgen-opc.c: Clean up pass over `struct foo' usage.
+ (cgen_keyword_lookup_value): Handle "" entry.
+ (cgen_keyword_add): Likewise.
+start-sanitize-cygnus
+ * Makefile.am: Add cgen support.
+ * Makefile.in: Regenerate.
+ * configure.in: Add cgen support.
+ * configure: Regenerate.
+ * aclocal.m4: Regenerate.
+ * cgen.sh, cgen-asm.in, cgen-dis.in: New files.
+end-sanitize-cygnus
+
+Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-opc.c: Add FP_D to s.d instruction flags.
+
+Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (halt, pulse): Enable them on the 68060.
+
+start-sanitize-tic80
+Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
+ PC relative offset forms before the 15 bit forms. An assembler command
+ line option now chooses the default.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Tue Dec 16 13:24:22 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c: Add many missing r5900 instructions.
+
+end-sanitize-r5900
+start-sanitize-d30v
+Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table): Set new flags bits
+ FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions.
+
+end-sanitize-d30v
+1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com>
+
+ * configure: Only build libopcodes shared if --enable-shared's value
+ was `yes', or was set to `*opcodes*'.
+ * aclocal.m4: Likewise.
+ * NOTE: this really needs to be fixed in libtool/libtool.m4, the
+ original source of this bit of code. It's not clear what the best fix
+ would be, though.
+
+start-sanitize-r5900
+Mon Dec 15 12:43:36 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.
+end-sanitize-r5900
+start-sanitize-tic80
+Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
+ (tic80_opcodes): Reorder table entries to put the 32 bit PC relative
+ offset forms before the 15 bit forms, to default to the long forms.
+
+end-sanitize-tic80
+Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
+
+Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (print_insn_little_arm): Prevent examination of stored
+ symbol if none is present.
+ (print_insn_big_arm): Prevent examination of stored symbol if
+ none is present.
+
+Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
+
+Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com>
+
+ * disassemble.c: Remove disasm_symaddr() function.
+
+ * arm-dis.c: Use info->symbol instead of info->flags to determine
+ if disassmbly should be in Thumb or Arm mode.
+
+Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c: Add support for disassembling Thumb opcodes.
+ (print_insn_thumb): New function.
+
+ * disassemble.c (disasm_symaddr): New function.
+
+ * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
+ (thumb_opcodes): Table of Thumb opcodes.
+
+Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (btst): Change Dd@s to Dd;b.
+
+ * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q',
+ and 'v' as operand types.
+
+Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add argument for lpstop. From Olivier Carmona
+ <olivier.carmona@di.epfl.ch>.
+ * m68k-dis.c (print_insn_m68k): Handle special case of lpstop,
+ which has a two word opcode with a one word argument.
+
+start-sanitize-d30v
+Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
+ unsigned, not signed.
+ (d30v_format_table): Add SHORT_CMPU cases for cmpu.
+
+end-sanitize-d30v
+start-sanitize-sh4
+Wed Nov 19 17:42:35 1997 Richard Henderson <rth@cygnus.com>
+
+ * sh-dis.c (print_insn_shx): Recognize all sh4 additions.
+ * sh-opc.h (fmov): Add @<REG_M>+,<DX_REG_N> variant for sh4.
+ (ftrv): Slay the cut-and-paste monster.
+
+end-sanitize-sh4
+Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-dis.c (print_operand):
+ Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
+
+Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-opc.c (OPERAND_FLAG): Split into:
+ (OPERAND_FFLAG, OPERAND_CFLAG) .
+ (FSRC): Split into:
+ (FFSRC, CFSRC).
+
+Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Move the INSN_MACRO ISA value to the membership
+ field for all INSN_MACRO's.
+ * mips16-opc.c: same
+
+Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (sync,cache): These are 3900 insns.
+
+Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ sh-opc.h (sh_table): Remove ftst/nan.
+
+start-sanitize-vr5400
+Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding.
+ (c.*.ob, mula.ob, mull.ob, muls.ob, mulsl.ob): Put 'k' version
+ last.
+ * mips-dis.c (print_insn_arg): Handle VR5400 operand types.
+
+end-sanitize-vr5400
+start-sanitize-tx49
+Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ Add tx49 insns and configury.
+
+end-sanitize-tx49
+Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (ffc, ffs): Fix mask.
+
+start-sanitize-d30v
+Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
+ control registers.
+
+end-sanitize-d30v
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+start-sanitize-vr5400
+ Added VR5400 instructions.
+ (N5): New cpu-id macro.
+end-sanitize-vr5400
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Replace // with /* ... */
+
+Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com>
+
+ * sparc-opc.c: Add wr & rd for v9a asr's.
+ * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.
+ (v9a_asr_reg_names): New variable.
+ Patch from David Miller <davem@vger.rutgers.edu>.
+
+Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com>
+
+ * sparc-opc.c (v9notv9a): New insn type.
+ (IMPDEP): Move to the end to not conflict with edge8 et al.
+ Patch from David Miller <davem@vger.rutgers.edu>.
+
+Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (bnezl,beqzl): Mark these as also tx39.
+
+Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
+
+Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Use new symbol_at_address_func() field
+ of disassemble_info structure to determine if an overlay address
+ has a matching symbol in low memory.
+
+ * dis-buf.c (generic_symbol_at_address): New (dummy) function for
+ new symbol_at_address_func field in disassemble_info structure.
+
+Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (extract_d22): Use signed arithmatic.
+
+Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Three op mult is not an ISA insn.
+
+Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Fix formatting.
+
+Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
+ than assuming that char is signed. Explicitly sign extend 16 bit
+ values, rather than assuming that short is 16 bits.
+ (OP_sI, OP_J, OP_DIR): Likewise.
+
+start-sanitize-v850e
+Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (v850_sreg_names): Use symbolic names for higher
+ system registers.
+
+end-sanitize-v850e
+Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Fix typo in comment.
+
+ * v850-dis.c (disassemble): Add test of processor type when
+ determining opcodes.
+
+Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Use a diversion to set enable_shared before the
+ arguments are parsed.
+ * configure: Rebuild.
+
+Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c (TBL1): Use ! rather than `.
+ * m68k-dis.c (print_insn_arg): Remove ` operand specifier.
+
Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com>
+ * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire.
+
+ * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32.
+
* m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
for mcf5200.
Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
- * configure (cgen_files): Add support for v850eq target.
- * configure.in (cgen_files): Add support for v850eq target.
+ * configure (cgen_files): Add support for v850ea target.
+ * configure.in (cgen_files): Add support for v850ea target.
end-sanitize-v850e
Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com>
Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com>
start-sanitize-v850e
- * v850-dis.c (disassemble): Add support for v850EQ instructions.
+ * v850-dis.c (disassemble): Add support for v850EA instructions.
* v850-opc.c (insert_i5div, extract_i5div): New Functions.
- (v850_opcodes): Add v850EQ instructions.
+ (v850_opcodes): Add v850EA instructions.
* v850-dis.c (disassemble): Add support for v850E instructions.
projects / deliverable / binutils-gdb.git / blobdiff