+2018-10-19 Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
+ (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
+ (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
+
+2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
+ corresponding to AARCH64_OPND_QLF_S_4B qualifier.
+
+2018-10-10 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
+ Size64. Add Size.
+ * i386-opc.h (Size16, Size32, Size64): Delete.
+ (Size): New.
+ (SIZE16, SIZE32, SIZE64): Define.
+ (struct i386_opcode_modifier): Drop size16, size32, and size64.
+ Add size.
+ * i386-opc.tbl (Size16, Size32, Size64): Define.
+ * i386-tbl.h: Re-generate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Add
+ SSBS in the check for one-bit immediate.
+ (aarch64_sys_regs): New entry for SSBS.
+ (aarch64_sys_reg_supported_p): New check for above.
+ (aarch64_pstatefields): New entry for SSBS.
+ (aarch64_pstatefield_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for
+ scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
+ (aarch64_sys_reg_supported_p): New checks for above.
+
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.