+2007-05-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4502
+ * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw".
+
+2007-05-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h (ShortForm): Redefined.
+ (Jump): Likewise.
+ (JumpDword): Likewise.
+ (JumpByte): Likewise.
+ (JumpInterSegment): Likewise.
+ (FloatMF): Likewise.
+ (FloatR): Likewise.
+ (FloatD): Likewise.
+ (Size16): Likewise.
+ (Size32): Likewise.
+ (Size64): Likewise.
+ (IgnoreSize): Likewise.
+ (DefaultSize): Likewise.
+ (No_bSuf): Likewise.
+ (No_wSuf): Likewise.
+ (No_lSuf): Likewise.
+ (No_sSuf): Likewise.
+ (No_qSuf): Likewise.
+ (No_xSuf): Likewise.
+ (FWait): Likewise.
+ (IsString): Likewise.
+ (regKludge): Likewise.
+ (IsPrefix): Likewise.
+ (ImmExt): Likewise.
+ (NoRex64): Likewise.
+ (Rex64): Likewise.
+ (Ugh): Likewise.
+
+2007-05-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries
+ for some SSE4 instructions.
+ (threebyte_0x3a_uses_DATA_prefix): Likewise.
+
+2007-05-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
+
+ * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
+ type for crc32.
+
+2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
+ check data size prefix in 16bit mode.
+
+ * i386-opc.c (i386_optab): Default crc32 to non-8bit and
+ support Intel mode.
+
+2007-04-30 Mark Salter <msalter@redhat.com>
+
+ * frv-desc.c: Regenerate.
+ * frv-desc.h: Regenerate.
+
+2007-04-30 Alan Modra <amodra@bigpond.net.au>
+
+ PR 4436
+ * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE.
+
+2007-04-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (modrm): Put reg before rm.
+
+2007-04-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4430
+ * i386-dis.c (print_displacement): New.
+ (OP_E): Call print_displacement instead of print_operand_value
+ to output displacement when either base or index exist. Print
+ the explicit zero displacement in 16bit mode.
+
+2007-04-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4429
+ * i386-dis.c (print_insn): Also swap the order of op_riprel
+ when swapping op_index. Break when the RIP relative address
+ is printed.
+ (OP_E): Properly handle RIP relative addressing and print the
+ explicit zero displacement for Intel mode.
+
+2007-04-27 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * ns32k-dis.c: Include sysdep.h first.
+
+2007-04-24 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the
+ opcode.
+ * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions.
+
+2007-04-24 Nick Clifton <nickc@redhat.com>
+
+ * arm-dis.c (print_insn): Initialise type.
+
+2007-04-24 Alan Modra <amodra@bigpond.net.au>
+
+ * cgen-types.h: Include bfd_stdint.h, not stdint.h.
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k-opc.c: Mark mcfisa_c instructions.
+
+2007-04-21 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-dis.c (arm_opcodes): Disassemble to unified syntax.
+ (thumb_opcodes): Add missing white space in adr.
+ (arm_decode_shift): New parameter, print_shift. Only decode the
+ shift parameter if set. Adjust callers.
+ (print_insn_arm): Support for operand type q with no shift decode.
+
+2007-04-21 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete.
+ Move contents to..
+ (i386_regtab): ..here.
+ * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
+
+ * ppc-opc.c (powerpc_operands): Delete duplicate entries.
+ (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
+ (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
+ (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
+
+2007-04-20 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
+ rambar1.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
+ change.
+ * ppc-opc.c (powerpc_operands): Replace bit count with bit mask
+ in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
+ references to following deleted functions.
+ (insert_bd, extract_bd, insert_dq, extract_dq): Delete.
+ (insert_ds, extract_ds, insert_de, extract_de): Delete.
+ (insert_des, extract_des, insert_li, extract_li): Delete.
+ (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
+ (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
+ (num_powerpc_operands): New constant.
+ (XSPRG_MASK): Remove entire SPRG field.
+ (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.
+ (Z2_MASK): Define.
+ (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
+
+2007-04-20 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-dis.c (print_insn): Only look for a mapping symbol in the section
+ being disassembled.
+
+2007-04-19 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2007-04-19 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,
+ db10cyc, db12cyc, db16cyc.
+
+2007-04-19 Nathan Froyd <froydnj@codesourcery.com>
+
+ * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.
+
+2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (CRC32_Fixup): New.
+ (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
+ PREGRP91): New.
+ (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
+ (threebyte_0x3a_uses_DATA_prefix): Likewise.
+ (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
+ PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
+ (three_byte_table): Likewise.
+
+ * i386-opc.c (i386_optab): Add SSE4.2 opcodes.
+
+ * i386-opc.h (CpuSSE4_2): New.
+ (CpuSSE4): Likewise.
+ (CpuUnknownFlags): Add CpuSSE4_2.
+
+2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (XMM_Fixup): New.
+ (Edqb): New.
+ (Edqd): New.
+ (XMM0): New.
+ (dqb_mode): New.
+ (dqd_mode): New.
+ (PREGRP39 ... PREGRP85): New.
+ (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
+ (threebyte_0x3a_uses_DATA_prefix): Likewise.
+ (prefix_user_table): Add PREGRP39 ... PREGRP85.
+ (three_byte_table): Likewise.
+ (putop): Handle 'K'.
+ (intel_operand_size): Handle dqb_mode, dqd_mode):
+ (OP_E): Likewise.
+ (OP_G): Likewise.
+
+ * i386-opc.c (i386_optab): Add SSE4.1 opcodes.
+
+ * i386-opc.h (CpuSSE4_1): New.
+ (CpuUnknownFlags): Add CpuSSE4_1.
+ (regKludge): Update comment.
+
+2007-04-18 Matthias Klose <doko@ubuntu.com>
+
+ * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion.
+ * Makefile.in: Regenerate.
+
+2007-04-14 Steve Ellcey <sje@cup.hp.com>
+
+ * Makefile.am: Add ACLOCAL_AMFLAGS.
+ * Makefile.in: Regenerate.
+
+2007-04-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c: Remove trailing white spaces.
+ * i386-opc.c: Likewise.
+ * i386-opc.h: Likewise.
+
+2007-04-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4333
+ * i386-dis.c (GRP1a): New.
+ (GRP1b ... GRPPADLCK2): Update index.
+ (dis386): Use GRP1a for entry 0x8f.
+ (mod, rm, reg): Removed. Replaced by ...
+ (modrm): This.
+ (grps): Add GRP1a.
+
2007-04-09 Kazu Hirata <kazu@codesourcery.com>
* m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and
projects / deliverable / binutils-gdb.git / blobdiff