+2000-03-27 Ian Lance Taylor <ian@zembu.com>
+
+ * Makefile.am (CFILES): Add avr-dis.c.
+ (ALL_MACHINES): Add avr-dis.lo.
+
+2000-03-27 Alan Modra <alan@linuxcare.com>
+
+ * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
+ truncate integers.
+ (print_insn_avr): Call function via pointer in K&R compatible way.
+ (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
+ add0fff, add03f8): Convert to old style function declaration and
+ add prototype.
+ (avrdis_opcode): Add prototype.
+
+2000-03-27 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c: New file. AVR disassembler.
+ * configure.in (bfd_avr_arch): New architecture support.
+ * disassemble.c: Likewise.
+ * configure: Regenerate.
+
+Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
+
+2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
+ flag to determine if operand is pc-relative.
+ * d30v-opc.c:
+ (d30v_format_table):
+ (REL6S3): Renamed from IMM6S3.
+ Added flag OPERAND_PCREL.
+ (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
+ added flag OPERAND_PCREL.
+ (IMM12S3U): Replaced with REL12S3.
+ (SHORT_D2, LONG_D): Delay target is pc-relative.
+ (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
+ Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
+ using the REL* operands.
+ (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
+ (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
+ LONG_Db, using REL* operands.
+ (SHORT_U, SHORT_A5S): Removed stray alternatives.
+ (d30v_opcode_table): Use new *r formats.
+
+2000-02-28 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
+ 'signed_overflow_ok_p'.
+
+2000-02-27 Eli Zaretskii <eliz@is.elta.co.il>
+
+ * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
+ name of the libtool directory.
+ * Makefile.in: Rebuild.
+
+2000-02-24 Nick Clifton <nickc@cygnus.com>
+
+ * cgen-opc.c (cgen_set_signed_overflow_ok): New function.
+ (cgen_clear_signed_overflow_ok): New function.
+ (cgen_signed_overflow_ok_p): New function.
+
+2000-02-23 Andrew Haley <aph@cygnus.com>
+
+ * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+ m32r-ibld.c,m32r-opc.h: Rebuild.
+
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * i370-dis.c, i370-opc.c: New.
+
+ * disassemble.c (ARCH_i370): Define.
+ (disassembler): Handle it.
+
+ * Makefile.am: Add support for Linux/IBM 370.
+ * configure.in: Likewise.
+
+ * Makefile.in: Regenerate.
+ * configure: Likewise.
+
+2000-02-22 Chandra Chavva <cchavva@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
+ ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
+ procedure.
+
+1999-12-30 Andrew Haley <aph@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
+ force gp32 to zero.
+ * mips-opc.c (G6): New define.
+ (mips_builtin_op): Add "move" definition for -gp32.
+
+2000-02-22 Ian Lance Taylor <ian@zembu.com>
+
+ From Grant Erickson <gerickso@Brocade.COM>:
+ * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
+
+2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * dis-buf.c (buffer_read_memory): Change `length' param and all int
+ vars to unsigned.
+
+Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
+ (print_insn_ppi): Likewise.
+ (print_insn_shx): Use info->mach to select appropriate insn set.
+ Add support for sh-dsp. Remove FD_REG_N support.
+ * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
+ (sh_arg_type): Likewise. Remove FD_REG_N.
+ (sh_dsp_reg_nums): New enum.
+ (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
+ (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
+ (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
+ (arch_sh3_dsp_up): Likewise.
+ (sh_opcode_info): New field: arch.
+ (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
+ D_REG_N. Fill in arch field. Add sh-dsp insns.
+
+2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>
+
+ * arm-dis.c: Change flavor name from atpcs-special to
+ special-atpcs to prevent name conflict in gdb.
+ (get_arm_regname_num_options, set_arm_regname_option,
+ get_arm_regnames): New functions. API to access the several
+ flavor of register names. Note: Used by gdb.
+ (print_insn_thumb): Use the register name entry from the currently
+ selected flavor for LR and PC.
+
+2000-02-10 Nick Clifton <nickc@cygnus.com>
+
+ * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
+ classes.
+ (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
+ "mulsh.h" instructions.
+ * mcore-dis.c (imsk array): Add masks for MULSH and OPSR
+ classes.
+ (print_insn_mcore): Add support for little endian targets.
+ Add support for MULSH and OPSR classes.
+
+2000-02-07 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (parse_arm_diassembler_option): Rename again.
+ Previous delat did not take.
+
2000-02-03 Timothy Wall <twall@redhat.com>
* dis-buf.c (buffer_read_memory): Use octets_per_byte field
projects / deliverable / binutils-gdb.git / blobdiff