+2019-11-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
+ entry.
+ (operand_types): Remove EsSeg entry.
+ (main): Replace stale use of OTMax.
+ * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
+ (struct i386_opcode_modifier): Expand isstring field to 2 bits.
+ (EsSeg): Delete.
+ (OTUnused): Comment out.
+ (union i386_operand_type): Remove esseg field.
+ * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
+ (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
+ (ins, movs, smov, movsd): Add IsStringEsOpOp1.
+ (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_instances): Add RegB entry.
+ * i386-opc.h (enum operand_instance): Add RegB.
+ * i386-opc.tbl (RegC, RegD, RegB): Define.
+ (Acc, ShiftCount, InOutPortReg): Adjust definitions.
+ (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
+ monitorx, mwaitx): Drop ImmExt and convert encodings
+ accordingly.
+ * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
+ (edx, rdx): Add Instance=RegD.
+ (ebx, rbx): Add Instance=RegB.
+ * i386-tbl.h: Re-generate.
+
+2019-11-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Adjust
+ OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
+ OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
+ OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
+ (operand_instances): New.
+ (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
+ (output_operand_type): New parameter "instance". Process it.
+ (process_i386_operand_type): New local variable "instance".
+ (main): Adjust static assertions.
+ * i386-opc.h (INSTANCE_WIDTH): Define.
+ (enum operand_instance): New.
+ (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
+ (union i386_operand_type): Replace acc, inoutportreg, and
+ shiftcount by instance.
+ * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
+ * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
+ Add Instance=.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-11 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
+ smaxp/sminp entries' "tied_operand" field to 2.
+
+2019-11-11 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Replace
+ "index" local variable by that of the already existing "num".
+
+2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25167
+ * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
+ * i386-tbl.h: Regenerated.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
+ OPERAND_TYPE_REGBND entry.
+ (operand_classes): Add RegMask and RegBND entries.
+ (operand_types): Drop RegMask and RegBND entry.
+ * i386-opc.h (enum operand_class): Add RegMask and RegBND.
+ (RegMask, RegBND): Delete.
+ (union i386_operand_type): Remove regmask and regbnd fields.
+ * i386-opc.tbl (RegMask, RegBND): Define.
+ * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
+ Class=RegBND.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
+ OPERAND_TYPE_REGZMM entries.
+ (operand_classes): Add RegMMX and RegSIMD entries.
+ (operand_types): Drop RegMMX and RegSIMD entries.
+ * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
+ (RegMMX, RegSIMD): Delete.
+ (union i386_operand_type): Remove regmmx and regsimd fields.
+ * i386-opc.tbl (RegMMX): Define.
+ (RegXMM, RegYMM, RegZMM): Add Class=.
+ * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
+ Class=RegSIMD.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
+ entries.
+ (operand_classes): Add RegCR, RegDR, and RegTR entries.
+ (operand_types): Drop Control, Debug, and Test entries.
+ * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
+ (Control, Debug, Test): Delete.
+ (union i386_operand_type): Remove control, debug, and test
+ fields.
+ * i386-opc.tbl (Control, Debug, Test): Define.
+ * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
+ Class=RegDR, and Test by Class=RegTR.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class= to
+ OPERAND_TYPE_SREG entry.
+ (operand_classes): Add SReg entry.
+ (operand_types): Drop SReg entry.
+ * i386-opc.h (enum operand_class): Add SReg.
+ (SReg): Delete.
+ (union i386_operand_type): Remove sreg field.
+ * i386-opc.tbl (SReg): Define.
+ * i386-reg.tbl: Replace SReg by Class=SReg.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Add Class=. New
+ OPERAND_TYPE_ANYIMM entry.
+ (operand_classes): New.
+ (operand_types): Drop Reg entry.
+ (output_operand_type): New parameter "class". Process it.
+ (process_i386_operand_type): New local variable "class".
+ (main): Adjust static assertions.
+ * i386-opc.h (CLASS_WIDTH): Define.
+ (enum operand_class): New.
+ (Reg): Replace by Class. Adjust comment.
+ (union i386_operand_type): Replace reg by class.
+ * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
+ Class=.
+ * i386-reg.tbl: Replace Reg by Class=Reg.
+ * i386-init.h: Re-generate.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
+ (aarch64_opcode_table): Add data gathering hint mnemonic.
+ * opcodes/aarch64-dis-2.c: Account for new instruction.
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
+
+
+2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
+ aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
+ aarch64_feature_f64mm): New feature sets.
+ (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
+ F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
+ instructions.
+ (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
+ macros.
+ (QL_MMLA64, OP_SVE_SBB): New qualifiers.
+ (OP_SVE_QQQ): New qualifier.
+ (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
+ F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
+ the movprfx constraint.
+ (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
+ (aarch64_opcode_table): Define new instructions smmla,
+ ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
+ uzip{1/2}, trn{1/2}.
+ * aarch64-opc.c (operand_general_constraint_met_p): Handle
+ AARCH64_OPND_SVE_ADDR_RI_S4x32.
+ (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
+ * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
+ Account for new instructions.
+ * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
+ S4x32 operand.
+ * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
+
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
projects / deliverable / binutils-gdb.git / blobdiff