+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
+ matching for INSN2_SHORT_ONLY opcode table entries.
+ * mips16-opc.c (SH): New macro.
+ (mips16_opcodes): Set SH in `pinfo2' for non-extensible
+ instruction entries: "nop", "addu", "and", "break", "cmp",
+ "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
+ "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
+ "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
+ "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
+ "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
+ "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
+ "seh", "sew", "zeb", "zeh", "zew" and "extend".
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
+ encoding support.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
+ "extend".
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (set_default_mips_dis_options): Use
+ HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
+ call to `bfd_mips_elf_get_abiflags'.
+ * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
+ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * Makefile.in: Regenerate.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * po/opcodes.pot: Regenerate.
+
+2016-12-21 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
+ ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
+ (print_insn_mips16): Check opcode entries for validity against
+ the ISA level and ASE set selected.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
+ `insn' together, with `extend' as the high-order 16 bits.
+ (match_kind): New enum.
+ (print_insn_mips16): Rework for 32-bit instruction matching.
+ Do not dump EXTEND prefixes here.
+ * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
+ Recode `match' and `mask' fields as 32-bit in absolute "jal" and
+ "jalx" entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
+ INSN_MACRO entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
+ opcode).
+
2016-12-20 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to