+2017-02-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PCMPESTR_Fixup): New.
+ (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
+ (prefix_table): Use PCMPESTR_Fixup.
+ (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
+ PCMPESTR_Fixup.
+ (vex_w_table): Delete VPCMPESTR{I,M} entries.
+ * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
+ Split 64-bit and non-64-bit variants.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
+ (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
+ (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
+ (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
+ (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
+ (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
+ (OP_SVE_V_HSD): New macros.
+ (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
+ (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
+ (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
+ (aarch64_opcode_table): Add new SVE instructions.
+ (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
+ for rotation operands. Add new SVE operands.
+ * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
+ (ins_sve_quad_index): Likewise.
+ (ins_imm_rotate): Split into...
+ (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
+ * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
+ (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
+ functions.
+ (aarch64_ins_sve_addr_ri_s4): New function.
+ (aarch64_ins_sve_quad_index): Likewise.
+ (do_misc_encoding): Handle "MOV Zn.Q, Qm".
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
+ (ext_sve_quad_index): Likewise.
+ (ext_imm_rotate): Split into...
+ (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
+ * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
+ (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
+ functions.
+ (aarch64_ext_sve_addr_ri_s4): New function.
+ (aarch64_ext_sve_quad_index): Likewise.
+ (aarch64_ext_sve_index): Allow quad indices.
+ (do_misc_decoding): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
+ aarch64_field_kinds.
+ (OPD_F_OD_MASK): Widen by one bit.
+ (OPD_F_NO_ZR): Bump accordingly.
+ (get_operand_field_width): New function.
+ * aarch64-opc.c (fields): Add new SVE fields.
+ (operand_general_constraint_met_p): Handle new SVE operands.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc-2.c: Regenerate.
+
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
+ (aarch64_feature_compnum): ...this.
+ (SIMD_V8_3): Replace with...
+ (COMPNUM): ...this.
+ (CNUM_INSN): New macro.
+ (aarch64_opcode_table): Use it for the complex number instructions.
+
+2017-02-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
+
+2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
+
+ Add support for associating SPARC ASIs with an architecture level.
+ * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
+ * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
+ decoding of SPARC ASIs.
+
+2017-02-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
+ 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
+
+2017-02-21 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
+ 1 (instead of to itself). Correct typo.
+
+2017-02-14 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+ pseudoinstructions.
+
+2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
+ (aarch64_sys_reg_supported_p): Handle them.
+
+2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (UIMM6_20R): Define.
+ (SIMM12_20): Use above.
+ (SIMM12_20R): Define.
+ (SIMM3_5_S): Use above.
+ (UIMM7_A32_11R_S): Define.
+ (UIMM7_9_S): Use above.
+ (UIMM3_13R_S): Define.
+ (SIMM11_A32_7_S): Use above.
+ (SIMM9_8R): Define.
+ (UIMM10_A32_8_S): Use above.
+ (UIMM8_8R_S): Define.
+ (W6): Use above.
+ (arc_relax_opcodes): Use all above defines.
+
+2017-02-15 Vineet Gupta <vgupta@synopsys.com>
+
+ * arc-regs.h: Distinguish some of the registers different on
+ ARC700 and HS38 cpus.
+
+2017-02-14 Alan Modra <amodra@gmail.com>
+
+ PR 21118
+ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
+ with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
+
+2017-02-11 Stafford Horne <shorne@gmail.com>
+ Alan Modra <amodra@gmail.com>
+
+ * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
+ Use insn_bytes_value and insn_int_value directly instead. Don't
+ free allocated memory until function exit.
+
+2017-02-10 Nicholas Piggin <npiggin@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
+
+2017-02-03 Nick Clifton <nickc@redhat.com>
+
+ PR 21096
+ * aarch64-opc.c (print_register_list): Ensure that the register
+ list index will fir into the tb buffer.
+ (print_register_offset_address): Likewise.
+ * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
+
+2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
+
+ PR 21056
+ * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
+ instructions when the previous fetch packet ends with a 32-bit
+ instruction.
+
+2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * pru-opc.c: Remove vague reference to a future GDB port.
+
+2017-01-20 Nick Clifton <nickc@redhat.com>
+
+ * po/ga.po: Updated Irish translation.
+
+2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
+
+2017-01-13 Yao Qi <yao.qi@linaro.org>
+
+ * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
+ if FETCH_DATA returns 0.
+ (m68k_scan_mask): Likewise.
+ (print_insn_m68k): Update code to handle -1 return value.
+
+2017-01-13 Yao Qi <yao.qi@linaro.org>
+
+ * m68k-dis.c (enum print_insn_arg_error): New.
+ (NEXTBYTE): Replace -3 with
+ PRINT_INSN_ARG_MEMORY_ERROR.
+ (NEXTULONG): Likewise.
+ (NEXTSINGLE): Likewise.
+ (NEXTDOUBLE): Likewise.
+ (NEXTDOUBLE): Likewise.
+ (NEXTPACKED): Likewise.
+ (FETCH_ARG): Likewise.
+ (FETCH_DATA): Update comments.
+ (print_insn_arg): Update comments. Replace magic numbers with
+ enum.
+ (match_insn_m68k): Likewise.
+
+2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
+ CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
+ * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
+ (i386_cpu_flags): Add cpuavx512_vpopcntdq.
+ * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2017-01-12 Yao Qi <yao.qi@linaro.org>
+
+ * msp430-dis.c (msp430_singleoperand): Return -1 if
+ msp430dis_opcode_signed returns false.
+ (msp430_doubleoperand): Likewise.
+ (msp430_branchinstr): Return -1 if
+ msp430dis_opcode_unsigned returns false.
+ (msp430x_calla_instr): Likewise.
+ (print_insn_msp430): Likewise.
+
+2017-01-05 Nick Clifton <nickc@redhat.com>
+
+ PR 20946
+ * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
+ could not be matched.
+ (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
+ NULL.
+
+2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
+ (aarch64_opcode_table): Use RCPC_INSN.
+
+2017-01-03 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
+ extension.
+ * riscv-opcodes/all-opcodes: Likewise.
+
+2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
+
+ * riscv-dis.c (print_insn_args): Add fall through comment.
+
+2017-01-03 Nick Clifton <nickc@redhat.com>
+
+ * po/sr.po: New Serbian translation.
+ * configure.ac (ALL_LINGUAS): Add sr.
+ * configure: Regenerate.
+
2017-01-02 Alan Modra <amodra@gmail.com>
* epiphany-desc.h: Regenerate.
projects / deliverable / binutils-gdb.git / blobdiff