Handle indirect branches for AMD64 and Intel64
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
index 31304b355f99eb71b03fb0f024613f24021d25dd..592b8b568f2d74fab27059f22acb24247722dd82 100644 (file)
@@ -1,3 +1,173 @@
+2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutis/18386
+       * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
+       (indir_v_mode): New.
+       Add comments for '&'.
+       (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
+       (putop): Handle '&'.
+       (intel_operand_size): Handle indir_v_mode.
+       (OP_E_register): Likewise.
+       * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
+       64-bit indirect call/jmp for AMD64.
+       * i386-tbl.h: Regenerated
+
+2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-dis.c (struct arc_operand_iterator): New structure.
+       (find_format_from_table): All the old content from find_format,
+       with some minor adjustments, and parameter renaming.
+       (find_format_long_instructions): New function.
+       (find_format): Rewritten.
+       (arc_insn_length): Add LSB parameter.
+       (extract_operand_value): New function.
+       (operand_iterator_next): New function.
+       (print_insn_arc): Use new functions to find opcode, and iterator
+       over operands.
+       * arc-opc.c (insert_nps_3bit_dst_short): New function.
+       (extract_nps_3bit_dst_short): New function.
+       (insert_nps_3bit_src2_short): New function.
+       (extract_nps_3bit_src2_short): New function.
+       (insert_nps_bitop1_size): New function.
+       (extract_nps_bitop1_size): New function.
+       (insert_nps_bitop2_size): New function.
+       (extract_nps_bitop2_size): New function.
+       (insert_nps_bitop_mod4_msb): New function.
+       (extract_nps_bitop_mod4_msb): New function.
+       (insert_nps_bitop_mod4_lsb): New function.
+       (extract_nps_bitop_mod4_lsb): New function.
+       (insert_nps_bitop_dst_pos3_pos4): New function.
+       (extract_nps_bitop_dst_pos3_pos4): New function.
+       (insert_nps_bitop_ins_ext): New function.
+       (extract_nps_bitop_ins_ext): New function.
+       (arc_operands): Add new operands.
+       (arc_long_opcodes): New global array.
+       (arc_num_long_opcodes): New global.
+       * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
+
+2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
+
+       * nds32-asm.h: Add extern "C".
+       * sh-opc.h: Likewise.
+
+2016-06-01  Graham Markall  <graham.markall@embecosm.com>
+
+       * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
+       0,b,limm to the rflt instruction.
+
+2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
+
+       * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
+       constant.
+
+2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/20145
+       * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
+       CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
+       CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
+       CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
+       CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
+       * i386-init.h: Regenerated.
+
+2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/20145
+       * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
+       CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
+       CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
+       Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
+       CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
+       CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
+       CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
+       Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
+       CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
+       CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
+       CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
+       for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
+       CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
+       CpuRegMask for AVX512.
+       (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
+       and CpuRegMask.
+       (set_bitfield_from_cpu_flag_init): New function.
+       (set_bitfield): Remove const on f.  Call
+       set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
+       * i386-opc.h (CpuRegMMX): New.
+       (CpuRegXMM): Likewise.
+       (CpuRegYMM): Likewise.
+       (CpuRegZMM): Likewise.
+       (CpuRegMask): Likewise.
+       (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
+       and cpuregmask.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/20154
+       * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
+       (opcode_modifiers): Add AMD64 and Intel64.
+       (main): Properly verify CpuMax.
+       * i386-opc.h (CpuAMD64): Removed.
+       (CpuIntel64): Likewise.
+       (CpuMax): Set to CpuNo64.
+       (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
+       (AMD64): New.
+       (Intel64): Likewise.
+       (i386_opcode_modifier): Add amd64 and intel64.
+       (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
+       on call and jmp.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/20154
+       * i386-gen.c (main): Fail if CpuMax is incorrect.
+       * i386-opc.h (CpuMax): Set to CpuIntel64.
+       * i386-tbl.h: Regenerated.
+
+2016-05-27  Nick Clifton  <nickc@redhat.com>
+
+       PR target/20150
+       * msp430-dis.c (msp430dis_read_two_bytes): New function.
+       (msp430dis_opcode_unsigned): New function.
+       (msp430dis_opcode_signed): New function.
+       (msp430_singleoperand): Use the new opcode reading functions.
+       Only disassenmble bytes if they were successfully read.
+       (msp430_doubleoperand): Likewise.
+       (msp430_branchinstr): Likewise.
+       (msp430x_callx_instr): Likewise.
+       (print_insn_msp430): Check that it is safe to read bytes before
+       attempting disassembly.  Use the new opcode reading functions.
+
+2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
+
+       * ppc-opc.c (CY): New define.  Document it.
+       (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
+
+2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
+       CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
+       and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
+       CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
+       CPU_ANY_AVX_FLAGS.
+       * i386-init.h: Regenerated.
+
+2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/20141
+       * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
+       CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
+       * i386-init.h: Regenerated.
+
+2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
+       CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
+       * i386-init.h: Regenerated.
+
 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
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